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    SEMICONDUCTOR OPTICAL DETECTOR STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR OPTICAL DETECTOR STRUCTURE 审中-公开

    公开(公告)号：WO2011005447A3

    公开(公告)日：2011-01-13

    申请号：PCT/US2010/039007

    申请日：2010-06-17

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DE SOUZA, Joel ,  HOVEL, Harold ,  INNS, Daniel ,  KIM, Jee ,  SADANA, Devendra

    Inventor： DE SOUZA, Joel ,  HOVEL, Harold ,  INNS, Daniel ,  KIM, Jee ,  SADANA, Devendra

    IPC: H01L31/0368 ,  H01L31/0392 ,  H01L31/072 ,  H01L31/18

    Abstract: A semiconductor is disclosed with a substrate doped with a substrate doping. There is a crystalline semiconductor layer disposed on a front side of the substrate. The crystalline semiconductor layer has a layer doping. The substrate doping changes to the layer doping within a 100 angstrom transition region. In alternative embodiments, the layer doping has novel profiles. In other alternative embodiments, the substrate has a crystalline semiconductor layers disposed on each of a front and a back side of the substrate. Each of the crystalline semiconductor layers has a respective layer doping and each of these layer dopings changes to the substrate doping within a respective transition region less than 100 angstroms thick. In still other embodiments of this invention, an amorphous silicon layer is disposed on a side of the crystalline semiconductor layer opposite the substrate. The amorphous silicon layer has an amorphous doping so that a tunnel junction is formed between the doped crystalline semiconductor layer and the amorphous layer. Manufacturing these structures at below 700 degrees Centigrade enables the narrow transition regions of the structures.

    THICK EPITAXIAL SILICON BY GRAIN REORIENTATION ANNEALING AND APPLICATIONS THEREOF
    3.
    发明申请
    THICK EPITAXIAL SILICON BY GRAIN REORIENTATION ANNEALING AND APPLICATIONS THEREOF 审中-公开
    通过颗粒重新形成的厚度大的外延硅及其应用

    公开(公告)号：WO2010060673A1

    公开(公告)日：2010-06-03

    申请号：PCT/EP2009/062918

    申请日：2009-10-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  SAENGER, Katherine ,  DE SOUZA, Joel ,  FOGEL, Keith ,  SADANA, Devendra ,  INNS, Daniel

    Inventor： SAENGER, Katherine ,  DE SOUZA, Joel ,  FOGEL, Keith ,  SADANA, Devendra ,  INNS, Daniel

    IPC: C30B1/02 ,  C30B29/06 ,  C23C16/56

    CPC classification number: C30B29/06 ,  C23C16/24 ,  C23C16/56 ,  C30B1/02

    Abstract: The invention provides a high temperature (about 1150 C or greater) annealing process for converting thick poly crystalline Si layers on the order of 1 μm to 40 μm on a single crystal seed layer into thick single crystal Si layers having the orientation of the seed layer, thus allowing production of thick Si films having the quality of single crystal silicon at high rates and low cost of processing. Methods of integrating such high temperature processing into solar cell fabrication are described, with particular attention to process flows in which the seed layer is disposed on a porous silicon release layer. Another aspect pertains to the use of similar high temperature anneals for poly-Si grain growth and grain boundary passivation. A further aspect relates to structures in which these thick single crystal Si films and passivated poly-Si films are incorporated.

    Abstract translation: 本发明提供了一种高温（约1150℃或更高）的退火工艺，用于将单晶种子层上的厚度为1μm至40μm的厚多晶硅层转化成具有晶种层取向的厚单晶Si层 ，因此能够以高速率生产具有单晶硅质量的厚Si薄膜，并且处理成本低。 描述了将这种高温处理集成到太阳能电池制造中的方法，特别注意种子层设置在多孔硅释放层上的工艺流程。 另一方面涉及对于多晶硅晶粒生长和晶界钝化使用类似的高温退火。 另一方面涉及其中结合有这些厚单晶Si膜和钝化多晶硅膜的结构。

    BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH K GATE DIELECTRICS
    5.
    发明申请
    BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH K GATE DIELECTRICS 审中-公开
    使用III-V复合半导体和高K栅介质的BURIED CHANNEL MOSFET

    公开(公告)号：WO2007149581A2

    公开(公告)日：2007-12-27

    申请号：PCT/US2007014684

    申请日：2007-06-25

    Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

    Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

    IPC: H01L21/336 ,  H01L29/778

    CPC classification number: H01L29/7787 ,  H01L29/66462

    Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

    Abstract translation: 含半导体的异质结构包括从下至上的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

    METHOD OF FORMING STRAINED SILICON MATERIALS WITH IMPROVED THERMAL CONDUCTIVITY
    6.
    发明申请
    METHOD OF FORMING STRAINED SILICON MATERIALS WITH IMPROVED THERMAL CONDUCTIVITY 审中-公开
    形成具有改善的导热性的应变硅材料的方法

    公开(公告)号：WO2006017640A1

    公开(公告)日：2006-02-16

    申请号：PCT/US2005/027691

    申请日：2005-08-04

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BEDELL, Stephen, W. ,  CHEN, Huajie ,  FOGEL, Keith ,  MITCHELL, Ryan, M. ,  SADANA, Devendra, K.

    Inventor： BEDELL, Stephen, W. ,  CHEN, Huajie ,  FOGEL, Keith ,  MITCHELL, Ryan, M. ,  SADANA, Devendra, K.

    IPC: H01L21/36

    CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

    Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer (41) of Si or Ge is deposited on a substrate (10) in a first depositing step; a second layer (42) of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer (50) having a plurality of Si layers and a plurality of Ge layers (41-44). The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer. The combined SiGe layer (50) is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer (61) on the combined SiGe layer (50); the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer (61) is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.

    Abstract translation: 公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。 在第一沉积步骤中，在衬底（10）上沉积Si或Ge的第一层（41） 另一元件的第二层（42）在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层（41-44）的组合SiGe层（50）。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比。 组合的SiGe层（50）的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。 该方法还可以包括在组合SiGe层（50）上沉积Si层（61）的步骤。 组合的SiGe层被表征为弛豫的SiGe层，并且Si层（61）是应变Si层。 对于SiGe层中的更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

    SiGe LATTICE ENGINEERING USING A COMBINATION OF OXIDATION THINNING AND EPITAXIAL REGROWTH
    7.
    发明申请
    SiGe LATTICE ENGINEERING USING A COMBINATION OF OXIDATION THINNING AND EPITAXIAL REGROWTH 审中-公开
    使用氧化稀释和外延注射的组合的SiGe LATTICE ENGINEERING

    公开(公告)号：WO2004109776A3

    公开(公告)日：2005-05-19

    申请号：PCT/US2004016903

    申请日：2004-05-28

    Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

    Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

    IPC: H01L21/20 ,  H01L21/762 ,  H01L21/306

    CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  Y10T428/12674

    Abstract: The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.

    Abstract translation: 本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。 该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值， 一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。 根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。

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