公开(公告)号：WO2012135494A2

公开(公告)日：2012-10-04

申请号：PCT/US2012/031202

申请日：2012-03-29

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus Corbal ,  SANS, Roger Espasa ,  GIRKAR, Milind Baburao ,  WU, Lisa K. ,  BRADFORD, Dennis R. ,  LEE, Victor W.

Inventor： SAN ADRIAN, Jesus Corbal ,  SANS, Roger Espasa ,  GIRKAR, Milind Baburao ,  WU, Lisa K. ,  BRADFORD, Dennis R. ,  LEE, Victor W.

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30192

Abstract: Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination.

Abstract translation: 描述了用于在计算机处理器中执行对准指令的系统，装置和方法的实施例。 在一些实施例中，对齐指令的执行导致将两个级联源的数据元素的选择性存储存储在目的地中。

公开(公告)号：WO2012134555A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/063590

申请日：2011-12-06

Applicant: INTEL CORPORATION ,  VALENTINE, Robert, C. ,  HUGHES, Christopher, J. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  TOLL, Bret ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon

Inventor： VALENTINE, Robert, C. ,  HUGHES, Christopher, J. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  TOLL, Bret ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3455 ,  G06F9/355 ,  G06F9/3555 ,  G06F9/383 ,  G06F9/3865

Abstract: Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask

Abstract translation: 描述了用于在计算机处理器中执行收集和散播步幅指令的系统，装置和方法的实施例。 在一些实施例中，收集步幅指令的执行导致根据写入掩码的位值的至少一些位置将条带数据元素从存储器有条件地存储到目的地寄存器中

公开(公告)号：WO2012134532A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/054303

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  VALENTINE, Robert, C. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  CAVIN, Robert, D. ,  TOLL, Bret, L. ,  DURAN, Santiago, Galan ,  WIEDEMEIER, Jeffrey, G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind, Baburao ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon ,  BRADFORD, Dennis, R. ,  OULD-AHMED-VALL, Elmoustapha ,  ABEL, James, C. ,  CHARNEY, Mark ,  ABRAHAM, Seth ,  SAIR, Suleyman ,  FORSYTH, Andrew, Thomas ,  YOUNT, Charles ,  WU, Lisa

Inventor： VALENTINE, Robert, C. ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  CAVIN, Robert, D. ,  TOLL, Bret, L. ,  DURAN, Santiago, Galan ,  WIEDEMEIER, Jeffrey, G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind, Baburao ,  GROCHOWSKI, Edward, Thomas ,  HALL, Jonathan, Cannon ,  BRADFORD, Dennis, R. ,  OULD-AHMED-VALL, Elmoustapha ,  ABEL, James, C. ,  CHARNEY, Mark ,  ABRAHAM, Seth ,  SAIR, Suleyman ,  FORSYTH, Andrew, Thomas ,  YOUNT, Charles ,  WU, Lisa

IPC: G06F9/30 ,  G06F9/305 ,  G06F9/06

CPC classification number: G06F9/30181 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Abstract translation: 一种向量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 指令集包括向量友好指令格式。 向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作， 基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

公开(公告)号：WO2012135494A3

公开(公告)日：2012-12-27

申请号：PCT/US2012031202

申请日：2012-03-29

Applicant: INTEL CORP ,  SAN ADRIAN JESUS CORBAL ,  SANS ROGER ESPASA ,  GIRKAR MILIND BABURAO ,  WU LISA K ,  BRADFORD DENNIS R ,  LEE VICTOR W

Inventor： SAN ADRIAN JESUS CORBAL ,  SANS ROGER ESPASA ,  GIRKAR MILIND BABURAO ,  WU LISA K ,  BRADFORD DENNIS R ,  LEE VICTOR W

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30192

Abstract: Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination.

Abstract translation: 描述了用于在计算机处理器中执行对准指令的系统，装置和方法的实施例。 在一些实施例中，对齐指令的执行导致将两个连接的源的数据元素的选择性存储存储在目的地中。

公开(公告)号：WO2012134558A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/064254

申请日：2011-12-09

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  VALENTINE, Robert, C. ,  DURAN, Santiago, Galan ,  WIEDEMEIR, Jeffrey, G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  LEE, Victor, W.

Inventor： SAN ADRIAN, Jesus, Corbal ,  SANS, Roger, Espasa ,  VALENTINE, Robert, C. ,  DURAN, Santiago, Galan ,  WIEDEMEIR, Jeffrey, G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind, Baburao ,  FORSYTH, Andrew, Thomas ,  LEE, Victor, W.

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30018 ,  G06F9/30043

Abstract: Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.

Abstract translation: 描述了用于在计算机处理器中执行展开和/或压缩指令的系统，装置和方法的实施例。 在一些实施例中，扩展指令的执行导致根据写入掩码的值来稀疏地存储在目的地的源的元素的选择，并将源的每个选择的数据元素作为稀疏数据元素存储到目的地 位置，其中目的地位置对应于指示要存储源的相应数据元素的每个写入位位置。