公开(公告)号：WO2010000624A1

公开(公告)日：2010-01-07

申请号：PCT/EP2009/057581

申请日：2009-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BUCHMANN, Peter ,  FERRAIOLO, Frank ,  GOWER, Kevin ,  REESE, Robert, James ,  RETTER, Eric, Eugene ,  SCHMATZ, Martin, Leo ,  SPEAR, Michael, Bradley ,  THOMSEN, Peter, Matthew ,  TROMBLEY, Michael, Raymond

Inventor： BUCHMANN, Peter ,  FERRAIOLO, Frank ,  GOWER, Kevin ,  REESE, Robert, James ,  RETTER, Eric, Eugene ,  SCHMATZ, Martin, Leo ,  SPEAR, Michael, Bradley ,  THOMSEN, Peter, Matthew ,  TROMBLEY, Michael, Raymond

IPC: G06F13/42

CPC classification number: G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

Abstract translation: 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

公开(公告)号：WO2003013001A3

公开(公告)日：2003-02-13

申请号：PCT/IB2002/002829

申请日：2002-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SCHMATZ, Martin ,  CRANFORD, Hayden, Clay ,  NORMAN, Vernon, Roberts

Inventor： SCHMATZ, Martin ,  CRANFORD, Hayden, Clay ,  NORMAN, Vernon, Roberts

IPC: H03L7/081

Abstract: The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

公开(公告)号：WO2004015869A8

公开(公告)日：2004-04-22

申请号：PCT/IB0302918

申请日：2003-06-27

Applicant: IBM ,  CRANFORD JR HAYDEN C ,  NORMAN VERNON R ,  SCHMATZ MARTIN

Inventor： CRANFORD JR HAYDEN C ,  NORMAN VERNON R ,  SCHMATZ MARTIN

IPC: H03L7/089 ,  H03L7/10 ,  H03L7/085

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L2207/06

Abstract: A phase locked loop circuit for generating a frequency-controlled output signal and a method for providing a frequency controlled output signal in a phase locked loop circuit are introduced. A controllable oscillator unit (260, 460) of said phase locked loop is operated for generating the output signal (261, 461). A frequency of said output signal (261, 461) is evoked by providing the oscillator unit (260, 460) with a first control signal (281, 381, 481) and with a second control signal (241, 341, 441). The first control signal (281, 381, 481) and the second control signal (241, 341, 441) are adapted automatically such that a given reference frequency is achieved in the output signal (261, 461).

Abstract translation: 引入了用于生成频率控制的输出信号的锁相环电路和用于在锁相环电路中提供频率控制的输出信号的方法。 所述锁相环的可控制的振荡器单元（260,460）被操作用于生成输出信号（261,461）。 通过向振荡器单元（260,460）提供第一控制信号（281,381,481）和第二控制信号（241,341,441）来引起所述输出信号（261,461）的频率。 第一控制信号（281,381,481）和第二控制信号（241,341,441）被自动调整，使得在输出信号（261,461）中实现给定的参考频率。

公开(公告)号：WO2004015869A1

公开(公告)日：2004-02-19

申请号：PCT/IB2003/002918

申请日：2003-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CRANFORD Jr., Hayden, C. ,  NORMAN, Vernon, R. ,  SCHMATZ, Martin

Inventor： CRANFORD Jr., Hayden, C. ,  NORMAN, Vernon, R. ,  SCHMATZ, Martin

IPC: H03L7/085

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L2207/06

Abstract: A phase locked loop circuit for generating a frequency-controlled output signal and a method for providing a frequency controlled output signal in a phase locked loop circuit are introduced. A controllable oscillator unit (260, 460) of said phase locked loop is operated for generating the output signal (261, 461). A frequency of said output signal (261, 461) is evoked by providing the oscillator unit (260, 460) with a first control signal (281, 381, 481) and with a second control signal (241, 341, 441). The first control signal (281, 381, 481) and the second control signal (241, 341, 441) are adapted automatically such that a given reference frequency is achieved in the output signal (261, 461).

Abstract translation: 引入了用于产生频率控制输出信号的锁相环电路和用于在锁相环电路中提供频率控制输出信号的方法。 操作所述锁相环的可控振荡器单元（260,460），以产生输出信号（261,461）。 通过向第一控制信号（281,381,481）和第二控制信号（241,341,441）提供振荡器单元（260,460）来引发所述输出信号（261,461）的频率。 第一控制信号（281,381,481）和第二控制信号（241,341,441）自动适配，使得在输出信号（261,461）中实现给定的参考频率。

公开(公告)号：WO2003013001A2

公开(公告)日：2003-02-13

申请号：PCT/IB2002/002829

申请日：2002-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SCHMATZ, Martin ,  CRANFORD, Hayden, Clay ,  NORMAN, Vernon, Roberts

Inventor： SCHMATZ, Martin ,  CRANFORD, Hayden, Clay ,  NORMAN, Vernon, Roberts

IPC: H03L7/081

CPC classification number: H03L7/091 ,  H03L7/0814 ,  H03L7/089 ,  H04L7/0331

Abstract: The invention is directed to a clock data recovery system for resampling a clock signal according to an incoming data signal. The clock data recovery system comprises a clock generator for generating the clock signal and a phase adjustment unit for generating sampling phases dependent on a phase adjustment control signal. It also comprises a data sampling unit operable to generate a stream of input samples and an edge detector for generating therefrom an internal early signal and an internal late signal. A phase adjustment control unit is disposed for generating under use of the early signal and the late signal the phase adjustment control signal. The phase adjustment control unit is feedable with an external early/late signal and/or comprises an output for delivering an export early/late signal.

Abstract translation: 本发明涉及一种用于根据输入数据信号重新采样时钟信号的时钟数据恢复系统。 时钟数据恢复系统包括用于产生时钟信号的时钟发生器和用于根据相位调整控制信号产生采样相位的相位调整单元。 它还包括可操作以产生输入样本流的数据采样单元和用于从其产生内部早期信号和内部<！ - SIPO - >信号的边缘检测器。 设置相位调整控制单元，用于在使用早期信号和迟
后信号的同时产生相位调整控制信号。 相位调整控制单元可以用外部的早/晚信号进行馈送，和/或包括用于递送出口早/晚信号的输出。

公开(公告)号：WO2009100976A3

公开(公告)日：2009-11-12

申请号：PCT/EP2009050819

申请日：2009-01-26

Applicant: IBM ,  FERRAIOLO FRANK ,  DREPS DANIEL ,  REESE ROBERT ,  SCHMATZ MARTIN

Inventor： FERRAIOLO FRANK ,  DREPS DANIEL ,  REESE ROBERT ,  SCHMATZ MARTIN

IPC: H04L25/03

CPC classification number: H04L25/03866

Abstract: A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.

Abstract translation: 可以包括通过通信网络连接的发射机，接收机的通信系统。 通信网络上的通信链路可以在发射机和接收机之间传送数据。 系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。 结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。

公开(公告)号：WO2009100976A2

公开(公告)日：2009-08-20

申请号：PCT/EP2009/050819

申请日：2009-01-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FERRAIOLO, Frank ,  DREPS, Daniel ,  REESE, Robert ,  SCHMATZ, Martin

Inventor： FERRAIOLO, Frank ,  DREPS, Daniel ,  REESE, Robert ,  SCHMATZ, Martin

IPC: H04L25/03

CPC classification number: H04L25/03866

Abstract: A communications system that may include a transmitter, a receiver, connected over a communications network. A communication link on the communications network may transfer data between the transmitter and the receiver. The system may also include a logic unit to scramble a plurality of portions of the data at the transmitter based upon the communication link and may unscramble the plurality of portions of the data at the receiver. As a result, the logic unit may provide improved performance of the communication link and/or reduced power consumption of the communication link.

Abstract translation: 可以包括通过通信网络连接的发射机，接收机的通信系统。 通信网络上的通信链路可以在发射机和接收机之间传送数据。 系统还可以包括逻辑单元，用于基于通信链路在发射机处对数据的多个部分进行加扰，并且可以在接收器处解扰数据的多个部分。 结果，逻辑单元可以提供通信链路的改进的性能和/或通信链路的降低的功耗。

公开(公告)号：WO2005086351A1

公开(公告)日：2005-09-15

申请号：PCT/EP2005/050806

申请日：2005-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  CRANFORD, Hayden, Jr. ,  NICHOLLS, Gareth, John ,  MODARESS-RAZAVI, Bobak ,  NORMAN, Vernon ,  SCHMATZ, Martin

Inventor： CRANFORD, Hayden, Jr. ,  NICHOLLS, Gareth, John ,  MODARESS-RAZAVI, Bobak ,  NORMAN, Vernon ,  SCHMATZ, Martin

IPC: H03L7/00

CPC classification number: H03L7/0814 ,  H03L7/07 ,  H04L2027/0065 ,  H04L2027/0067

Abstract: Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.

Abstract translation: 描述了在高速串行链路中提供对频偏的自动适配的方面。 通过检测第一信号中的趋势来产生第二信号来调整在接收机链路中进行相位调整的第一信号，第二信号通过相位调整来提高对频偏的补偿率。 包括一个向上/向下计数器，用于通过串行接收器的时钟数据恢复环来对信号进行相位调整。 加法器耦合到上/下计数器并输出指示相位调整趋势的累加数据。 耦合到加法器的组合逻辑基于累积数据来适配信号。