公开(公告)号：WO2007104027A2

公开(公告)日：2007-09-13

申请号：PCT/US2007063603

申请日：2007-03-08

Applicant: QUALCOMM INC ,  SEVERSON MATTHEW LEVI ,  BURKE JOSEPH PATRICK ,  POTTIER PHILIP

Inventor： SEVERSON MATTHEW LEVI ,  BURKE JOSEPH PATRICK ,  POTTIER PHILIP

IPC: G06F11/36

CPC classification number: G06F11/3656

Abstract: A method of performing a debug operation on a processor after a power collapse is provided. An idle state of the processor is detected during an execution mode of the processor. The idle state is determined to be associated with a power collapse event. A debug state of the processor is restored by loading debug registers within the processor during the execution mode.

Abstract translation: 提供了在电源崩溃之后在处理器上执行调试操作的方法。 在处理器的执行模式期间检测处理器的空闲状态。 空闲状态被确定为与功率崩溃事件相关联。 在执行模式期间，通过在处理器中加载调试寄存器来恢复处理器的调试状态。

公开(公告)号：WO2006088762A3

公开(公告)日：2007-03-01

申请号：PCT/US2006004891

申请日：2006-02-10

Applicant: QUALCOMM INC ,  CHUA-EOAN LEW G ,  SEVERSON MATTHEW LEVI ,  DOBRE SORIN ADRIAN ,  PETROV TSVETOMIR P ,  GOEL RAJAT

Inventor： CHUA-EOAN LEW G ,  SEVERSON MATTHEW LEVI ,  DOBRE SORIN ADRIAN ,  PETROV TSVETOMIR P ,  GOEL RAJAT

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract translation: 集成电路包括多个电源域。 电源电流开关电路（SCSC）分布在每个电源域上。 当SCSC中的控制节点上存在信号时，SCSC将电源域的本地电源总线耦合到全局电源总线。 使能信号路径延伸穿过SCSC，使得使能信号可以从SCSC链从传播控制节点传播到控制节点，从而逐个转换SCSC。 当域要加电时，控制电路断言使第一链SCSC向下传播的使能信号。 在可编程的时间量之后，控制电路断言向下传播第二链的第二使能信号。 通过随着时间推移SCSC的接通，避免了将局部和全局总线连接在一起的大电流。

公开(公告)号：WO2005119914A1

公开(公告)日：2005-12-15

申请号：PCT/US2005/018831

申请日：2005-05-27

Applicant: QUALCOMM INCORPORATED ,  SEVERSON, Matthew, Levi ,  CHEN, Chih-tung ,  SHIPPEE, Geoffrey ,  DOBRE, Sorin

Inventor： SEVERSON, Matthew, Levi ,  CHEN, Chih-tung ,  SHIPPEE, Geoffrey ,  DOBRE, Sorin

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract translation: 通常，本公开涉及用于在用于电力管理的ASIC中实现头戴式开关和脚踏开关的电路。 所公开的电路不仅支持有效的电源管理，而且还有效地利用ASIC区域，降低复杂性以及使用电子设计自动化（EDA）工具。 以这种方式，所公开的电路可以支持增强的性能和简化的ASIC设计。 在一些情况下，头开关或脚踏开关电路可以实现为围绕形成ASIC核心的一部分的宏宏延伸的开关板环。 在其他情况下，通过将耦合到标准单元行的金属层功率路由嵌入分布式头部开关或脚踏开关组件，可将头开关或脚踏开关电路分布在ASIC内部。

公开(公告)号：WO2013009918A1

公开(公告)日：2013-01-17

申请号：PCT/US2012/046314

申请日：2012-07-11

Applicant: QUALCOMM INCORPORATED ,  SEVERSON, Matthew Levi

Inventor： SEVERSON, Matthew Levi

IPC: H03K23/66 ,  G06F1/14 ,  G06F1/32 ,  H04W52/02

CPC classification number: H03K23/66 ,  G06F1/12 ,  G06F1/14

Abstract: A shared real-time counter is configured to provide an accurate counter output based on a fast clock period when driven by a fast clock signal or by a slow clock signal. Combinational logic circuitry provides glitch free switching between a fast clock signal input to the counter and a slow clock input to the counter. The counter is always on and increases its count by an appropriate rational number of counts representing fast clock cycles for every cycle of the fast clock while in a fast clock mode, and by an appropriate rational number of fast clock periods for every cycle of the slow clock signal while in a slow clock mode.

Abstract translation: 共享实时计数器被配置为当由快速时钟信号或慢时钟信号驱动时，基于快速时钟周期提供精确的计数器输出。 组合逻辑电路在输入到计数器的快速时钟信号和计数器的慢时钟输入之间提供无毛刺切换。 计数器始终处于开启状态，并且在快速时钟模式下，通过适当的合理数量的计数表示快速时钟的每个周期，并且通过适当的有理数量的快速时钟周期来增加其计数，以使每个周期的慢 时钟信号，而在慢时钟模式。

公开(公告)号：WO2007104027A3

公开(公告)日：2007-09-13

申请号：PCT/US2007/063603

申请日：2007-03-08

Applicant: QUALCOMM INCORPORATED ,  SEVERSON, Matthew, Levi ,  BURKE, Joseph, Patrick ,  POTTIER, Philip

Inventor： SEVERSON, Matthew, Levi ,  BURKE, Joseph, Patrick ,  POTTIER, Philip

IPC: G06F11/36

Abstract: A method of performing a debug operation on a processor after a power collapse is provided. An idle state of the processor is detected during an execution mode of the processor. The idle state is determined to be associated with a power collapse event. A debug state of the processor is restored by loading debug registers within the processor during the execution mode.

公开(公告)号：WO2006088762A2

公开(公告)日：2006-08-24

申请号：PCT/US2006/004891

申请日：2006-02-10

Applicant: QUALCOMM Incorporated ,  CHUA-EOAN, Lew G. ,  SEVERSON, Matthew Levi ,  DOBRE, Sorin Adrian ,  PETROV, Tsvetomir P. ,  GOEL, Rajat

Inventor： CHUA-EOAN, Lew G. ,  SEVERSON, Matthew Levi ,  DOBRE, Sorin Adrian ,  PETROV, Tsvetomir P. ,  GOEL, Rajat

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.

Abstract translation: 集成电路包括多个电源域。 电源电流开关电路（SCSC）分布在每个电源域上。 当SCSC中的控制节点上存在信号时，SCSC将电源域的本地电源总线耦合到全局电源总线。 使能信号路径延伸穿过SCSC，使得使能信号可以从SCSC链从传播控制节点传播到控制节点，从而逐个转换SCSC。 当域要加电时，控制电路断言使第一链SCSC向下传播的使能信号。 在可编程的时间量之后，控制电路断言向下传播第二链的第二使能信号。 通过随着时间推移SCSC的接通，避免了将局部和全局总线连接在一起的大电流。