公开(公告)号：WO1999023776A1

公开(公告)日：1999-05-14

申请号：PCT/SG1997000055

申请日：1997-10-31

Applicant: SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD. ,  SGS-THOMSON MICROELECTRONICS S.A. ,  HUI, Yau, Wei, Lucas ,  LABORIE, Jean, Louis ,  LASSURE, Gaël

Inventor： SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD. ,  SGS-THOMSON MICROELECTRONICS S.A.

IPC: H04J03/06

CPC classification number: H04J3/0632 ,  H04L2012/5616 ,  H04L2012/5681

Abstract: Apparatus for depacketizing and aligning packetized input data. Data processing means (305) receives the input data via an input memory (301) and detects, identifies and determines payload size of a data packet of the input data. The data processing means (305) generates a payload size signal indicative of the size of the payload. A word formatter (303) receives units of the payload from the input memory (301) and gathers and aligns these to form data words. A payload counter (306) controls flow of input data from the input memory (301) to the word formatter (303) in accordance with the payload size signal. An input buffer (304) receives the data words from the word formatter (303), stores these and transfers them to the data processing means (305) for effecting data processing.

Abstract translation: 用于解包和对齐分组化输入数据的装置。 数据处理装置（305）经由输入存储器（301）接收输入数据，并检测并识别输入数据的数据分组的有效负载大小。 数据处理装置（305）产生指示有效负载大小的有效载荷大小信号。 单词格式化器（303）从输入存储器（301）接收有效载荷的单元，并收集并对齐它们以形成数据字。 有效载荷计数器（306）根据有效负载大小信号控制输入数据从输入存储器（301）到字格式化器（303）的流程。 输入缓冲器（304）从字格式化器（303）接收数据字，存储这些数据字并将其传送到数据处理装置（305）以进行数据处理。

公开(公告)号：WO1998029996A1

公开(公告)日：1998-07-09

申请号：PCT/FR1997002465

申请日：1997-12-30

Applicant: SGS-THOMSON MICROELECTRONICS S.A.

Inventor： SGS-THOMSON MICROELECTRONICS S.A. ,  MESTDAGH, Denis, J., G.

IPC: H04L27/26

CPC classification number: H04L27/2623 ,  H04L27/2626

Abstract: The invention concerns a system for formatting a signal (s(t), (DMTin) in multicarrier modulation, which consists in clipping (18) the signal, in amplitude, with respect to a threshold value (Aclip), and in re-injecting (10), with delay and on a signal to be formatted, a clipping noise (clip) redistributed (19), at least partially, outside the used frequency band (f1-f2) of the multicarrier modulation signal.

Abstract translation: 本发明涉及用于对多载波调制中的信号（s（t），（DMTin））进行格式化的系统，其包括以幅度相对于阈值（Aclip）来限幅（18）信号，并且在重新注入 （10）至少部分地在所述多载波调制信号的所述使用频带（f1-f2）之外重新分配（19）的剪切噪声（剪辑）被延迟并且将要被格式化的信号。

公开(公告)号：WO1998019463A1

公开(公告)日：1998-05-07

申请号：PCT/GB1997002984

申请日：1997-10-29

Applicant: SGS-THOMSON MICROELECTRONICS LIMITED ,  COLE, Anthony, James, Carvallo

Inventor： SGS-THOMSON MICROELECTRONICS LIMITED

IPC: H04N07/50

CPC classification number: H04N19/423 ,  H04N19/61

Abstract: According to the present invention circuitry is provided for processing digital data items. The circuitry comprises compression and decompression circuitry. The compression circuitry further comprises: a circuit for transforming M number of data items into N number of data items; a circuit for quantising P number of data items and producing Q number of data items; and a circuitry for appropriately storing in memory and/or transferring R number of data items. The decompression circuitry comprises: a circuit for appropriately retrieving from memory and/or receiving S number of data items; a circuit for dequantising T number of data items and producing U number of dequantised data items; and a circuit for receiving and inverse transforming V number of data items into W number of data items, said W data items being representative of said M data items.

Abstract translation: 根据本发明，提供了用于处理数字数据项的电路。 电路包括压缩和解压缩电路。 压缩电路还包括：用于将M个数据项变换成N个数据项的电路; 用于量化P个数据项并产生Q个数据项的电路; 以及用于适当地存储在存储器中和/或传送R个数据项的电路。 解压缩电路包括：用于从存储器适当地检索和/或接收S个数据项的电路; 用于逆量化T个数据项并产生U个解量化数据项的电路; 以及用于接收并将V个数据项逆变换为W个数据项的电路，所述W个数据项表示所述M个数据项。

公开(公告)号：WO1998018230A3

公开(公告)日：1998-04-30

申请号：PCT/SG1997000046

申请日：1997-09-26

Applicant: SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD ,  HUI, Yau, Wai, Lucas

Inventor： SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD

IPC: H04H01/00

公开(公告)号：WO1990010559A1

公开(公告)日：1990-09-20

申请号：PCT/IT1990000023

申请日：1990-03-06

Applicant: ROLTRA-MORSE S.P.A. ,  SGS-THOMSON MICROELECTRONICS S.R.L. ,  BRUSASCO, Enzo ,  BOERO, Giuseppe ,  STORTI, Sandro ,  MURARI, Bruno

Inventor： ROLTRA-MORSE S.P.A. ,  SGS-THOMSON MICROELECTRONICS S.R.L.

IPC: B60R16/02

CPC classification number: B60R16/0315 ,  B60R2016/0322

Abstract: A system for controlling a number of electric devices (14, 15, 17, 18, 28, 28'; 19) on a car (1), particularly those fitted to the vehicle door (2, 2', 3, 3') and comprising at least a window regulator (18), a door lock device (17), a manual control push-button device (14) and a device (15) for electrically controlling an external rearview mirror (16); which devices (14, 15, 17, 18, 28, 28'; 19) comprise at least an electric operating member (24), and which system comprises at least a central processing unit (5) and at least a cable (7, 7', 8, 8') for electrically connecting the central processing unit (5) to the devices (14, 15, 17, 18, 28, 28'; 19); a single electric connecting cable (7, 7', 8, 8') being provided for the devices (14, 15, 17, 18) on each door (2, 2', 3, 3'), and comprising a first wire (10) for supplying positive electrical power, a second wire (11) for transmitting information signals, and a third ground wire (12); which information signals are transmitted over the aforementioned second wire (11) in asynchronous, serial manner; and which devices (14, 15, 17, 18, 28, 28'; 19) comprise a specific electronic control block (27) comprising at least a first integrated circuit (23) for supplying electrical power for operating the aforementioned member (24), and a second integrated circuit (25) for processing information signals relative to operation of the same.

Abstract translation: 一种用于控制轿厢（1）上的多个电气设备（14,15,17,18,28,28'; 19）的系统，特别是安装在车门（2,2'，3'）上的那些装置 并且至少包括窗口调节器（18），门锁装置（17），手动控制按钮装置（14）和用于电控制外部后视镜（16）的装置（15）。 所述装置（14,15,17,18,28,28'; 19）至少包括电操作构件（24），并且该系统至少包括中央处理单元（5）和至少一个电缆（7， 用于将中央处理单元（5）电连接到设备（14,15,17,18,28,28'; 19）上的7'，8,8'; 为每个门（2,2'，3,3'）上的设备（14,15,17,18）提供单个电连接电缆（7,7'，8,8'），并且包括第一线 （10），用于发送正电力的第二电线（11）和用于发送信息信号的第二电线（11）和第三接地线（12）。 哪些信息信号以异步串行方式在上述第二线路（11）上传输; 以及哪些装置（14,15,17,18,28,28'; 19）包括特定的电子控制块（27），该电子控制块包括用于提供用于操作上述构件（24）的电力的至少第一集成电路（23） ，以及用于处理相对于其操作的信息信号的第二集成电路（25）。

公开(公告)号：WO1998019407A3

公开(公告)日：1998-05-07

申请号：PCT/SG1997000045

申请日：1997-09-26

Applicant: SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD ,  HUI, Yau, Wai, Lucas ,  GEORGE, Sapna

Inventor： SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD

IPC: H04H01/00

公开(公告)号：WO1998009471A1

公开(公告)日：1998-03-05

申请号：PCT/GB1997002338

申请日：1997-08-29

Applicant: SGS-THOMSON MICROELECTRONICS LIMITED ,  THOMSON-CSF

Inventor： SGS-THOMSON MICROELECTRONICS LIMITED ,  THOMSON-CSF ,  SIMPSON, Robert ,  RICHARDS, Neil ,  THOMPSON, Peter ,  MONIOT, Pascal ,  COPPOLA, Marcello ,  DUMAS, Pierre ,  GRENOT, Thierry ,  MOUEN MAKOUA, David

IPC: H04Q11/04

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/1553 ,  H04L49/255 ,  H04L2012/563 ,  H04L2012/5647 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5681 ,  H04Q11/0478

Abstract: An ATM routing switch for bidirectional transmission of at least two types of cell (61), one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity (160) for cells of the first type, a second reserve buffer capacity (150) for cells of said second type and control circuitry (39, 40, 41) for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity (160) is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity (150) has been reached by input of cells of said second type.

Abstract translation: 用于至少两种类型的小区（61）的双向传输的ATM路由交换机，接收可变比特率传输的一种类型和接收传输中的小区的一些丢失的第二类型，包括用于所述小区的小区的第一预备缓冲器容量（160） 第一类型，用于所述第二类型的单元的第二预留缓冲器容量（150）和用于产生流量控制信号（FCT）的控制电路（39,40,41），如果达到所述第一缓冲器容量（160）的预定阈值 通过输入所述第一类型的单元，并且如果通过所述第二类型的单元的输入已经达到了用于所述第二缓冲器容量（150）的预定阈值，则丢弃所述第二类型的输入单元。

公开(公告)号：WO1998009470A1

公开(公告)日：1998-03-05

申请号：PCT/GB1997002331

申请日：1997-08-29

Applicant: SGS-THOMSON MICROELECTRONICS LIMITED ,  THOMSON-CSF

Inventor： SGS-THOMSON MICROELECTRONICS LIMITED ,  THOMSON-CSF ,  SIMPSON, Robert ,  RICHARDS, Neil ,  THOMPSON, Peter ,  MONIOT, Pascal ,  COPPOLA, Marcello ,  COTTIGNIES, Vincent ,  DUMAS, Pierre ,  MOUEN MAKOUA, David

IPC: H04Q11/04

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/255 ,  H04L49/256 ,  H04L2012/563 ,  H04L2012/5647 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04Q11/0478

Abstract: An ATM routing switch (21) has a buffer circuit (35) for holding cells located on queues at output ports (30), the buffer having a first reserve buffer capacity (161, 162) for cells of a first type requiring integrity of cell transmission and a first designation for use in determining a permitted path through the network, a second reserve buffer capacity (163, 164) for cells of the first type having a second designation for use in determining a different permitted path in the network and a third reserve buffer capacity (150) for cells of a second type accepting some loss of cells in transmission, flow control circuitry operating to limit input of cells of either the first or second type if predetermined thresholds for the first, second or third buffer capacities are reached.

Abstract translation: ATM路由交换机（21）具有用于保存位于输出端口（30）上的队列上的小区的缓冲电路（35），该缓冲器具有用于要求单元格完整性的第一类型的单元的第一备用缓冲器容量（161,162） 传输和用于确定通过网络的允许路径的第一指定;第一类型的小区的第二预留缓冲器容量（163,164）具有用于确定网络中的不同允许路径的第二指定，以及第三 如果达到第一，第二或第三缓冲器容量的预定阈值，流量控制电路用于限制第一或第二类型的单元的输入，流量控制电路接收第二类型的单元的预留缓冲器容量（150） 。

公开(公告)号：WO1997049087A1

公开(公告)日：1997-12-24

申请号：PCT/IT1996000198

申请日：1996-10-30

Applicant: SGS-THOMSON MICROELECTRONICS S.R.L. ,  ROLANDI, Paolo

Inventor： SGS-THOMSON MICROELECTRONICS S.R.L.

IPC: G11C11/56

CPC classification number: G11C11/5621 ,  G11C5/145 ,  G11C11/5642 ,  G11C16/30

Abstract: A multi-level memory circuit for binary information, according to the invention, comprises a plurality (MTX) of memory cells, each adapted to store more than one item of binary information and comprised of at least one floating gate MOS transistor, the information stored therein corresponding to the level of the cell threshold voltage, and a read voltage generating circuit (ALIM) for the cell plurality, adapted to be input a supply voltage (VCC). The generating circuit (ALIM) includes a voltage boosting circuit (CHP) adapted to generate a read voltage (VW) having a higher value than the value of the supply voltage (VCC).

Abstract translation: 根据本发明的用于二进制信息的多级存储器电路包括多个（MTX）存储器单元，每个存储单元适于存储多于一个的二进制信息项，并且包括至少一个浮置栅极MOS晶体管，所存储的信息 其中对应于单元阈值电压的电平，以及适用于输入电源电压（VCC）的单元多个的读取电压产生电路（ALIM）。 发生电路（ALIM）包括适于产生具有比电源电压（VCC）的值更高的值的读取电压（VW）的升压电路（CHP）。

公开(公告)号：WO1997025668A1

公开(公告)日：1997-07-17

申请号：PCT/FR1997000035

申请日：1997-01-09

Applicant: SGS-THOMSON MICROELECTRONICS S.A. ,  MONIER, Guy

Inventor： SGS-THOMSON MICROELECTRONICS S.A.

IPC: G06F07/72

CPC classification number: G06F7/728 ,  G06F7/535 ,  G06F2207/5353

Abstract: A modular arithmetic coprocessor for performing calculations according to the Montgomery method, and comprising a division circuit for performing integer divisions. The integer division circuit calculates the division of binary data A coded over n' + n" bits by binary data B coded over n bits, with A, B, n, n' and n" being integers other than zero. For this functionality, the division circuit comprises first and second n-bit registers for containing binary data A and the division result, a third n-bit register for containing an intermediate result, a fourth n-bit register for containing binary data B, two subtracting circuits each having first and second serial inputs and a serial output, and a test circuit having an input and an output.

Abstract translation: 一种用于根据蒙哥马利方法执行计算的模数算术协处理器，并且包括用于执行整数除法的分割电路。 整数分割电路通过在n位编码的二进制数据B，计算对n'+ n“位进行编码的二进制数据A的除法，其中A，B，n，n'和n”是除零之外的整数。 对于该功能，分频电路包括用于包含二进制数据A和除法结果的第一和第二n位寄存器，用于包含中间结果的第三n位寄存器，用于包含二进制数据B的第四n位寄存器，二 每个具有第一和第二串行输入和串行输出的减法电路以及具有输入和输出的测试电路。