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    METHOD AND DEVICE FOR FORMATTING A CLIPPING NOISE IN A MULTICARRIER MODULATION
    1.
    发明申请
    METHOD AND DEVICE FOR FORMATTING A CLIPPING NOISE IN A MULTICARRIER MODULATION 审中-公开
    用于在多媒体调制中形成剪辑噪声的方法和装置

    公开(公告)号：WO1998029996A1

    公开(公告)日：1998-07-09

    申请号：PCT/FR1997002465

    申请日：1997-12-30

    Applicant: SGS-THOMSON MICROELECTRONICS S.A.

    Inventor： SGS-THOMSON MICROELECTRONICS S.A. ,  MESTDAGH, Denis, J., G.

    IPC: H04L27/26

    CPC classification number: H04L27/2623 ,  H04L27/2626

    Abstract: The invention concerns a system for formatting a signal (s(t), (DMTin) in multicarrier modulation, which consists in clipping (18) the signal, in amplitude, with respect to a threshold value (Aclip), and in re-injecting (10), with delay and on a signal to be formatted, a clipping noise (clip) redistributed (19), at least partially, outside the used frequency band (f1-f2) of the multicarrier modulation signal.

    Abstract translation: 本发明涉及用于对多载波调制中的信号（s（t），（DMTin））进行格式化的系统，其包括以幅度相对于阈值（Aclip）来限幅（18）信号，并且在重新注入 （10）至少部分地在所述多载波调制信号的所述使用频带（f1-f2）之外重新分配（19）的剪切噪声（剪辑）被延迟并且将要被格式化的信号。

    MODULAR ARITHMETIC COPROCESSOR COMPRISING AN INTEGER DIVISION CIRCUIT
    2.
    发明申请
    MODULAR ARITHMETIC COPROCESSOR COMPRISING AN INTEGER DIVISION CIRCUIT 审中-公开
    包含整数分组电路的模块化算法协同处理器

    公开(公告)号：WO1997025668A1

    公开(公告)日：1997-07-17

    申请号：PCT/FR1997000035

    申请日：1997-01-09

    Applicant: SGS-THOMSON MICROELECTRONICS S.A. ,  MONIER, Guy

    Inventor： SGS-THOMSON MICROELECTRONICS S.A.

    IPC: G06F07/72

    CPC classification number: G06F7/728 ,  G06F7/535 ,  G06F2207/5353

    Abstract: A modular arithmetic coprocessor for performing calculations according to the Montgomery method, and comprising a division circuit for performing integer divisions. The integer division circuit calculates the division of binary data A coded over n' + n" bits by binary data B coded over n bits, with A, B, n, n' and n" being integers other than zero. For this functionality, the division circuit comprises first and second n-bit registers for containing binary data A and the division result, a third n-bit register for containing an intermediate result, a fourth n-bit register for containing binary data B, two subtracting circuits each having first and second serial inputs and a serial output, and a test circuit having an input and an output.

    Abstract translation: 一种用于根据蒙哥马利方法执行计算的模数算术协处理器，并且包括用于执行整数除法的分割电路。 整数分割电路通过在n位编码的二进制数据B，计算对n'+ n“位进行编码的二进制数据A的除法，其中A，B，n，n'和n”是除零之外的整数。 对于该功能，分频电路包括用于包含二进制数据A和除法结果的第一和第二n位寄存器，用于包含中间结果的第三n位寄存器，用于包含二进制数据B的第四n位寄存器，二 每个具有第一和第二串行输入和串行输出的减法电路以及具有输入和输出的测试电路。

    APPARATUS AND METHOD FOR DEPACKETIZING AND ALIGNING PACKETIZED INPUT DATA
    6.
    发明申请
    APPARATUS AND METHOD FOR DEPACKETIZING AND ALIGNING PACKETIZED INPUT DATA 审中-公开
    用于封装和排序封装输入数据的装置和方法

    公开(公告)号：WO1999023776A1

    公开(公告)日：1999-05-14

    申请号：PCT/SG1997000055

    申请日：1997-10-31

    Applicant: SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD. ,  SGS-THOMSON MICROELECTRONICS S.A. ,  HUI, Yau, Wei, Lucas ,  LABORIE, Jean, Louis ,  LASSURE, Gaël

    Inventor： SGS-THOMSON MICROELECTRONICS ASIA PACIFIC (PTE) LTD. ,  SGS-THOMSON MICROELECTRONICS S.A.

    IPC: H04J03/06

    CPC classification number: H04J3/0632 ,  H04L2012/5616 ,  H04L2012/5681

    Abstract: Apparatus for depacketizing and aligning packetized input data. Data processing means (305) receives the input data via an input memory (301) and detects, identifies and determines payload size of a data packet of the input data. The data processing means (305) generates a payload size signal indicative of the size of the payload. A word formatter (303) receives units of the payload from the input memory (301) and gathers and aligns these to form data words. A payload counter (306) controls flow of input data from the input memory (301) to the word formatter (303) in accordance with the payload size signal. An input buffer (304) receives the data words from the word formatter (303), stores these and transfers them to the data processing means (305) for effecting data processing.

    Abstract translation: 用于解包和对齐分组化输入数据的装置。 数据处理装置（305）经由输入存储器（301）接收输入数据，并检测并识别输入数据的数据分组的有效负载大小。 数据处理装置（305）产生指示有效负载大小的有效载荷大小信号。 单词格式化器（303）从输入存储器（301）接收有效载荷的单元，并收集并对齐它们以形成数据字。 有效载荷计数器（306）根据有效负载大小信号控制输入数据从输入存储器（301）到字格式化器（303）的流程。 输入缓冲器（304）从字格式化器（303）接收数据字，存储这些数据字并将其传送到数据处理装置（305）以进行数据处理。

    POWER SUPPLY CIRCUIT WITH A STORAGE CAPACITOR
    7.
    发明申请
    POWER SUPPLY CIRCUIT WITH A STORAGE CAPACITOR 审中-公开
    具有存储电容器的电源电路

    公开(公告)号：WO1997026701A1

    公开(公告)日：1997-07-24

    申请号：PCT/FR1997000089

    申请日：1997-01-17

    Applicant: SGS-THOMSON MICROELECTRONICS S.A. ,  MOREAU, Jean-Michel

    Inventor： SGS-THOMSON MICROELECTRONICS S.A.

    IPC: H02M01/12

    CPC classification number: H02M1/4208 ,  Y02B70/126

    Abstract: A power supply circuit with a storage capacitor is disclosed. The circuit includes a storage capacitor (C1) connected across the terminals of a rectifier bridge (1) and combined with a charging path and a discharging path. The charging path includes a predetermined-value current limiter (10, 10') controllable according to the voltage across the terminals of the rectifier bridge and the voltage across the terminals of the storage capacitor, whereby the storage capacitor is charged with a substantially constant current during each of the charging phases thereof.

    Abstract translation: 公开了一种具有存储电容器的电源电路。 电路包括连接在整流桥（1）的端子两端并与充电路径和放电路径组合的存储电容器（C1）。 充电路径包括根据整流桥两端的电压和存储电容器的端子两端的电压可控的预定值限流器（10,10'），由此对存储电容器充电基本恒定的电流 在其每个充电阶段期间。

    ELECTRONIC POWER SUPPLY DEVICE
    8.
    发明申请
    ELECTRONIC POWER SUPPLY DEVICE 审中-公开
    电子电源设备

    公开(公告)号：WO1996037038A1

    公开(公告)日：1996-11-21

    申请号：PCT/FR1996000740

    申请日：1996-05-15

    Applicant: SGS-THOMSON MICROELECTRONICS S.A. ,  WUIDART, Luc

    Inventor： SGS-THOMSON MICROELECTRONICS S.A.

    IPC: H02M01/00

    CPC classification number: H02M1/4266 ,  H02M1/32 ,  Y02B70/123 ,  Y02P80/112

    Abstract: A power factor correction circuit (3) has a first rectifier diode (D4) for controlling the serial charging of two capacitors (C1, C2), two rectifier diodes (D5, D6) for controlling the parallel discharging of the two capacitors, and a resistor (R) connected in series with the first diode (D4) in order to enhance the power factor and reduce the power-on current. An electronic current-controlled switch (T1) is used, and the parallel discharge diodes (D6, D5) are Zener diodes for protecting the load circuit against over-voltages just above the peak line voltage value.

    Abstract translation: 功率因数校正电路（3）具有用于控制两个电容器（C1，C2）的串联充电的第一整流二极管（D4），用于控制两个电容器的并联放电的两个整流二极管（D5，D6），以及 电阻器（R）与第一二极管（D4）串联连接，以增强功率因数并降低上电电流。 使用电子电流控制开关（T1），并联放电二极管（D6，D5）是齐纳二极管，用于保护负载电路免受高于峰值电压值的过电压。

    DEVICE FOR DIGITALLY CARRYING OUT A DIVISION OPERATION
    9.
    发明申请
    DEVICE FOR DIGITALLY CARRYING OUT A DIVISION OPERATION 审中-公开
    用于数字执行部门操作的设备

    公开(公告)号：WO1995032465A1

    公开(公告)日：1995-11-30

    申请号：PCT/FR1995000655

    申请日：1995-05-18

    Applicant: SGS-THOMSON MICROELECTRONICS S.A. ,  CURTET, Joël

    Inventor： SGS-THOMSON MICROELECTRONICS S.A.

    IPC: G06F07/52

    CPC classification number: G06F7/535 ,  G06F2207/5352

    Abstract: Device for digitally carrying out a binary division according to a method of non recovery of partial remainders. The device mainly comprises a circuit for detecting null partial remainders (COND) during the division operation. Advantageously, the combinatory circuits (3, 5) are provided for calculating a correction bit (CS2) to correct the quotient using a single command. Finally a circuit (10) is advantageously provided to calculate at each division step, the bit of the complemented quotient for the following divion step, and a multiplexer (2) for introducing at the following step, the opposite of the complemented quotient bit on the less significant position of the quotient. The device of the invenion is applicable to signal processors.

    Abstract translation: 根据部分余数的非恢复方法数字执行二进制除法的装置。 该装置主要包括用于在分割操作期间检测零部分余数（COND）的电路。 有利地，提供组合电路（3,5）以用于计算校正位（CS2），以使用单个命令校正商。 最后，有利地提供电路（10）以在每个划分步骤处计算以下分离步骤的互补商的比特和用于在下一步骤中引入与之相反的商数比特的多路复用器（2） 商的较不重要的位置。 该装置适用于信号处理器。

    METHOD AND TEST PLATFORMS FOR THE DEVELOPMENT OF AN INTEGRATED CIRCUIT (ASIC)
    10.
    发明申请
    METHOD AND TEST PLATFORMS FOR THE DEVELOPMENT OF AN INTEGRATED CIRCUIT (ASIC) 审中-公开
    用于集成电路（ASIC）开发的方法和测试平台

    公开(公告)号：WO1993024881A1

    公开(公告)日：1993-12-09

    申请号：PCT/FR1993000517

    申请日：1993-05-27

    Applicant: SGS-THOMSON MICROELECTRONICS S.A.

    Inventor： SGS-THOMSON MICROELECTRONICS S.A. ,  BONA, Mariano ,  COMTE, Pierre-Albert ,  PHAM-MINH, Duc

    IPC: G06F11/00

    CPC classification number: G06F11/3652 ,  G06F11/261

    Abstract: Method and test platforms for the development of an integrated circuit (1) to be used in an application incorporating on the same chip: a signal processor (2), a RAM memory (4), a ROM memory (3) for receiving control software and processing software and specific input/output control peripherals of the application (5). The signal processor (2), the RAM memory (4) and the ROM memory (3) correspond respectively to existing discrete components. The processing software is developped and tested on a test platform including at least said discrete components by means of interface software that controls the platform and automatic test sequencing from a microcomputer.

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