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    Method for fabricating a precision aligned semiconductor array
    3.
    发明授权
    Method for fabricating a precision aligned semiconductor array 失效
    制造精密对准半导体阵列的方法

    公开(公告)号：US3913216A

    公开(公告)日：1975-10-21

    申请号：US37174373

    申请日：1973-06-20

    Applicant: SIGNETICS CORP

    Inventor： BALLONOFF AARON

    IPC: H01L21/00 ,  H01L21/78 ,  B01J17/00

    CPC classification number: H01L21/78 ,  H01J9/233 ,  H01L21/00

    Abstract: A method for fabricating a precision aligned semiconductor array. In a specific embodiment, the method is applied to forming an array of semiconductor diodes useful as an electron bombarded semiconductor target. A wafer is fabricated with the semiconductor devices or circuits spaced on the wafer as they will be in the final array. After completion of fabrication of the devices the wafer has metallization formed on its back. The array is then bonded to metallized pads carried by an insulating substrate. After bonding the array to the substrate, a laser scriber removes a strip of material between adjacent devices so that there is no longer a continuous path of semiconductor between any two devices.

    Abstract translation: 一种制造精密对准半导体阵列的方法。 在具体实施例中，该方法被应用于形成用作电子轰击半导体靶的半导体二极管阵列。 制造晶圆，其中半导体器件或电路在晶片上间隔开，因为它们将处于最终阵列。 在器件的制造完成之后，晶片在其背面形成金属化。 然后将阵列结合到由绝缘衬底承载的金属化衬垫。 在将阵列结合到衬底之后，激光划刻器在相邻器件之间移除一条材料条，使得在任何两个器件之间不再有连续的半导体路径。

    High voltage bipolar semiconductor device and integrated circuit using the same and method
    5.
    发明授权
    High voltage bipolar semiconductor device and integrated circuit using the same and method 失效
    高电压双极半导体器件及使用该方法的集成电路

    公开(公告)号：US3836998A

    公开(公告)日：1974-09-17

    申请号：US37242773

    申请日：1973-06-21

    Applicant: SIGNETICS CORP

    Inventor： POLATA B ,  KOCSIS J

    IPC: H01L21/00 ,  H01L27/07 ,  H01L29/00 ,  H01L29/06 ,  H01L29/40 ,  H01L19/00

    CPC classification number: H01L29/404 ,  H01L21/00 ,  H01L27/0716 ,  H01L27/0733 ,  H01L29/00

    Abstract: Planar bipolar semiconductor device in which a substantial portion of the collector base junction is covered by an insulating layer and has a layer of metallization overlying a substantial portion of the collector region to cause the depletion layer to be moved into the bulk of the semiconductor body and to be spread over a large area whereby the electric field is greatly reduced to cause breakdown to take place within the semiconductor body rather than at the surface. In an integrated circuit, the bipolar device is isolated by the use of dielectric isolation.

    Abstract translation: 平面双极半导体器件，其中集电极基极结的大部分被绝缘层覆盖，并且具有覆盖在集电极区域的大部分上的金属化层，以使耗尽层移动到半导体本体的本体中， 扩散到大面积的区域，由此电场大大减小，从而在半导体本体而不是在表面处发生击穿。 在集成电路中，双极器件通过使用绝缘隔离来隔离。

    Process for making integrated circuit masks
    7.
    发明授权
    Process for making integrated circuit masks 失效
    制造集成电路面罩的工艺

    公开(公告)号：US3663223A

    公开(公告)日：1972-05-16

    申请号：US3663223D

    申请日：1969-05-13

    Applicant: SIGNETICS CORP

    Inventor： CAMENZIND HANS R

    IPC: G03F1/90 ,  H01L21/00 ,  G03C5/00

    CPC classification number: G03F1/90 ,  H01L21/00

    Abstract: Process for making a mask for integrated circuits in which a drawing is prepared of each standard pattern required in the circuit. A plurality of positive copies are prepared of each drawing with the number of positive copies being equal to the number of times the standard pattern is repeated in the integrated circuit. The positive copies are arranged on a sheet of substantially transparent dimensionally stable material and then secured in the desired positions. The non-standard parts are then drawn onto the sheet for interconnecting the standard patterns to provide a composite pattern for the integrated circuit. The composite pattern is then utilized for producing a negative of the pattern for the integrated circuit. The assembly consists of the substantially transparent, dimensionally stable sheet which has fastened thereto positive copies of the standard patterns with interconnecting circuitry drawn on the sheet.

    Abstract translation: 制造用于集成电路的掩模的工艺，其中制备电路中所需的每种标准图案的图形。 准备多个正副本，其中正副本的数量等于在集成电路中重复标准图案的次数的每个图。 阳性拷贝被布置在基本上透明的尺寸稳定的材料的片材上，然后固定在期望的位置。 然后将非标准部件拉伸到片材上以互连标准图案以提供用于集成电路的复合图案。 然后将复合图案用于产生用于集成电路的图案的负值。 该组件由基本上透明的尺寸稳定的片材组成，该片材已经固定在标准图案的正面副本上，并在片材上绘制了互连电路。

    Three output level logic circuit
    8.
    发明授权
    Three output level logic circuit 失效
    三输出电平逻辑电路

    公开(公告)号：US3602733A

    公开(公告)日：1971-08-31

    申请号：US3602733D

    申请日：1969-04-16

    Applicant: SIGNETICS CORP

    Inventor： AOKI EDWARD M

    IPC: H03K19/082 ,  H03K19/08

    CPC classification number: H03K19/0826

    Abstract: A three-output level logic circuit in which in addition to zero and one binary logic levels a third off-logic level is provided in which the output impedance is relatively high to in effect isolate the switching circuit from a common line to which it is connected thereby allowing several switching circuits to be used in common without deleteriously affecting switching speed in an overall computer or calculator unit.

    Testing apparatus for electrical device where a stimulus is varied between two states
    9.
    发明授权
    Testing apparatus for electrical device where a stimulus is varied between two states 失效
    电气设备的测试装置，两个国家之间的刺激是变化的

    公开(公告)号：US3581198A

    公开(公告)日：1971-05-25

    申请号：US3581198D

    申请日：1969-01-08

    Applicant: SIGNETICS CORP

    Inventor： SHOEMAKER WILLIAM E ,  WILSON DAVID W

    IPC: G01R31/00 ,  G01R27/28 ,  G01R31/26 ,  G01R15/12

    CPC classification number: G01R27/28 ,  G01R31/26

    Abstract: Testing apparatus for testing electrical devices such as operational amplifiers which sequences through a series of tests each test having first and second test halves during which a parameter of the device is varied between two states. The apparatus can be used for pass-fail testing of electrical devices or alternatively for sorting by selective display of the quantitative test information for any desired parameter. This is accomplished by providing a pushbutton for each test; by depressing the pushbutton associated with the test the quantitative information is displayed.

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