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    SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE
    1.
    发明申请
    SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE 审中-公开
    作为检测到的错误率的功能将功率节制作为电源

    公开(公告)号：WO2012134652A3

    公开(公告)日：2012-11-22

    申请号：PCT/US2012025526

    申请日：2012-02-16

    Applicant: QUALCOMM INC ,  CHUN DEXTER T ,  WOLF JACK K ,  SUH JUNGWON ,  SOWLATI TIRDAD

    Inventor： CHUN DEXTER T ,  WOLF JACK K ,  SUH JUNGWON ,  SOWLATI TIRDAD

    IPC: H03M9/00 ,  H04W52/02

    CPC classification number: H04L12/12 ,  H04L1/0001 ,  H04L1/0036 ,  H04L25/02 ,  H04W52/0209 ,  Y02D70/00

    Abstract: A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.

    Abstract translation: 系统涉及从第一集成电路（IC）到第二IC的第一SerDes链路以及从第二IC到第一IC的第二链路。 调整第一链路的电路中的功率消耗设置以控制功率消耗，使得第一链路的误码率保持在范围的下限基本上大于零的范围内。 调整用于第二链路的电路中的功率消耗设置以控制功率消耗，使得第二链路的误码率保持在范围内，其范围的下限基本上大于零。 在一个示例中，第二IC中的电路检测第一链路中的错误并通过第二链路报告。 第一个IC使用报告的信息来确定第一个链路的误码率。

    DIRECT CONVERSION RECEIVER HAVING A SUBHARMONIC MIXER
    3.
    发明申请
    DIRECT CONVERSION RECEIVER HAVING A SUBHARMONIC MIXER 审中-公开
    直接转换接收器具有亚音频混合器

    公开(公告)号：WO2007038482A3

    公开(公告)日：2007-12-13

    申请号：PCT/US2006037420

    申请日：2006-09-26

    Applicant: SKYWORKS SOLUTIONS INC ,  SOWLATI TIRDAD ,  PULLELA RAJASEKHAR ,  ROZENBLIT DMITRIY

    Inventor： SOWLATI TIRDAD ,  PULLELA RAJASEKHAR ,  ROZENBLIT DMITRIY

    IPC: H04B1/26

    CPC classification number: H04B1/30

    Abstract: A differential radio frequency (RF) receiver includes a fully differential direct conversion receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a differential radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired receive LO signals.

    Abstract translation: 差分射频（RF）接收器包括全差分直接转换接收链，接收链中的次谐波混频器，次谐波混频器被配置为接收差分射频（RF）输入信号和本地振荡器（LO）信号，该本地振荡器 以标称45度相移，以及具有压控振荡器并具有至少一个分频器的合成器，以产生期望的接收LO信号。

    DOWNCONVERTING MIXER
    4.
    发明申请
    DOWNCONVERTING MIXER 审中-公开
    DOWNCONVERTING混合器

    公开(公告)号：WO2007047540A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2006040281

    申请日：2006-10-13

    Applicant: SKYWORKS SOLUTIONS INC ,  PULLELA RAJA ,  YE PEIHUA ,  SOWLATI TIRDAD

    Inventor： PULLELA RAJA ,  YE PEIHUA ,  SOWLATI TIRDAD

    IPC: H04B1/26

    CPC classification number: H03D7/18 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0047

    Abstract: A downconverter is provided. The downconverter includes a I mixer and a Q mixer. Each mixer includes a transconductance stage and a mixer core stage. The outputs of the transconductance stages of the mixers are shorted together, and a resistors are arranged in series with an input of the mixer core stages.

    Abstract translation: 提供下变频器。 下变频器包括一个I混频器和一个Q混频器。 每个混频器都包含一个跨导级和一个混频器核心级。 混频器的跨导级的输出端一起短路，电阻器与混频器核心级的输入端串联。

    POLAR LOOP RADIO FREQUENCY (RF) TRANSMITTER HAVING INCREASED DYNAMIC RANGE AMPLITUDE CONTROL
    6.
    发明申请
    POLAR LOOP RADIO FREQUENCY (RF) TRANSMITTER HAVING INCREASED DYNAMIC RANGE AMPLITUDE CONTROL 审中-公开
    具有增加的动态范围电平控制的极性无线射频（RF）发射机

    公开(公告)号：WO2007008873A2

    公开(公告)日：2007-01-18

    申请号：PCT/US2006/026849

    申请日：2006-07-12

    Applicant: SKYWORKS SOLUTIONS, INC. ,  ROZENBLIT, Dmitriy ,  SOWLATI, Tirdad ,  DAMGAARD, Morten

    Inventor： ROZENBLIT, Dmitriy ,  SOWLATI, Tirdad ,  DAMGAARD, Morten

    IPC: H03D1/24 ,  H04L25/49 ,  H04L27/04

    CPC classification number: H04L27/3809 ,  H03C1/00 ,  H03G3/3047 ,  H04L27/08 ,  H04L27/361 ,  H04W52/06 ,  H04W52/36

    Abstract: A closed loop power control system for a radio frequency (RF) transmitter comprises a first variable gain element located in a power control loop and configured to receive a power level signal and an inverse representation of a power control signal, a second variable gain element located in the power control loop and configured to receive an error signal and the power control signal, and a third variable gain element configured to receive an amplitude modulated (AM) signal and the power control signal, the third variable gain element having a gain characteristic configured to operate to reduce the gain applied to the AM signal when the power control signal falls below a minimum predetermined value, and to provide the AM signal as a reference signal.

    Abstract translation: 用于射频（RF）发射机的闭环功率控制系统包括位于功率控制环路中并被配置为接收功率电平信号和功率控制信号的反向表示的第一可变增益元件，位于 在所述功率控制回路中并且被配置为接收误差信号和所述功率控制信号，以及第三可变增益元件，被配置为接收幅度调制（AM）信号和所述功率控制信号，所述第三可变增益元件具有被配置的增益特性 以在功率控制信号低于最小预定值时降低施加到AM信号的增益，并且提供AM信号作为参考信号。

    QUADRATURE SUBHARMONIC MIXER
    7.
    发明申请
    QUADRATURE SUBHARMONIC MIXER 审中-公开
    正品亚麻混合机

    公开(公告)号：WO2006014238A3

    公开(公告)日：2006-07-27

    申请号：PCT/US2005022182

    申请日：2005-06-23

    Applicant: SKYWORKS SOLUTIONS INC ,  SOWLATI TIRDAD

    Inventor： SOWLATI TIRDAD

    IPC: H04B1/26 ,  H04B1/10 ,  H04B1/16 ,  H04B15/00

    CPC classification number: H04B1/30 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/165 ,  H03D2200/0023 ,  H03D2200/0047

    Abstract: A quadrature subharmonic mixer comprises a polyphase filter configured to generate quadrature components of a local oscillator (LO) reference signal, a summing and scaling element configured to create additional components of the (LO) reference signal, and a plurality of mixer elements configured to multiply the quadrature components of the (LO) reference signal and the additional components of the (LO) reference signal with a radio frequency (RF) signal to obtain a downconverted version of the RF signal.

    Abstract translation: 正交次谐波混频器包括被配置为产生本地振荡器（LO）参考信号的正交分量的多相滤波器，被配置为产生（LO）参考信号的附加分量的求和和比例元素，以及多个混频器元件， （LO）参考信号的正交分量和具有射频（RF）信号的（LO）参考信号的附加分量，以获得RF信号的下变频版本。

    FULL DIGITAL BANG BANG FREQUENCY DETECTOR WITH NO DATA PATTERN DEPENDENCY
    8.
    发明申请
    FULL DIGITAL BANG BANG FREQUENCY DETECTOR WITH NO DATA PATTERN DEPENDENCY 审中-公开
    全数字BANG BANG频率检测器，无数据模式依赖

    公开(公告)号：WO2012097103A1

    公开(公告)日：2012-07-19

    申请号：PCT/US2012/020995

    申请日：2012-01-11

    Applicant: QUALCOMM Incorporated ,  KONG, Xiaohua ,  DANG, Nam V. ,  SOWLATI, Tirdad ,  AGGARWAL, Ashutosh

    Inventor： KONG, Xiaohua ,  DANG, Nam V. ,  SOWLATI, Tirdad ,  AGGARWAL, Ashutosh

    IPC: H04L7/033 ,  H03L7/087 ,  H03L7/089

    CPC classification number: H04L7/033 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0995

    Abstract: A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

    Abstract translation: 提供了一种没有数据模式依赖性的爆轰频率检测器。 在示例中，检测器从接收的数据恢复时钟，例如具有不归零（NRZ）格式的数据。 第一个爆炸相位检测器（BBPD）提供关于采样时钟和嵌入在接收数据中的时钟之间的相位差的第一阶段信息。 第二BBPD提供关于嵌入在接收数据中的时钟与采样时钟的延迟版本之间的第二相位差的第二阶段信息。 基于第一和第二相位差来确定采样时钟和嵌入在接收数据中的时钟之间的频率差。 频率差可用于调整采样时钟的频率。 锁定检测器可以耦合到BBPD输出，以确定采样时钟是否锁定在嵌入在接收数据中的时钟。

    SYSTEM AND METHOD FOR SATURATION DETECTION AND COMPENSATION IN A POLAR TRANSMITTER
    9.
    发明申请
    SYSTEM AND METHOD FOR SATURATION DETECTION AND COMPENSATION IN A POLAR TRANSMITTER 审中-公开
    用于饱和传感器中的饱和度检测和补偿的系统和方法

    公开(公告)号：WO2007133466A3

    公开(公告)日：2008-08-28

    申请号：PCT/US2007010731

    申请日：2007-05-03

    Applicant: SKYWORKS SOLUTIONS INC ,  ROZENBLIT DMITRIY ,  SOWLATI TIRDAD ,  AGAHI DARIOUSH ,  DAMGAARD MORTEN

    Inventor： ROZENBLIT DMITRIY ,  SOWLATI TIRDAD ,  AGAHI DARIOUSH ,  DAMGAARD MORTEN

    IPC: H01Q11/12

    CPC classification number: H03G3/3047

    Abstract: A system for saturation detection and compensation in a power amplifier includes a power amplifier, a closed power control loop configured to develop a power control signal (V PC ), a comparator configured to receive the power control signal and a reference signal, the comparator also configured to determine whether the power amplifier is operating in a saturation mode, and power control circuitry configured to reduce the power control signal if the power amplifier is operating in a saturation mode.

    Abstract translation: 功率放大器中的饱和检测和补偿系统包括：功率放大器，被配置为开发功率控制信号的闭合功率控制回路;配置成接收功率控制信号的比较器;以及 参考信号，所述比较器还被配置为确定所述功率放大器是否工作在饱和模式;以及功率控制电路，其被配置为如果所述功率放大器在饱和模式下工作，则降低所述功率控制信号。

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