TCET EXPANDER
    1.
    发明申请
    TCET EXPANDER 审中-公开
    TCET扩展器

    公开(公告)号:WO2004057431A3

    公开(公告)日:2005-04-07

    申请号:PCT/EP0312167

    申请日:2003-10-31

    Inventor: STAIGER DIETER E

    Abstract: The present invention relates to the field of embedded processing systems and electronic control units (ECUs)and to autonomic embedded computing solutions. The present invention proposes to remove or extract the application-specific support functions and respective I/O subsystems from the main processors or controllers of the system, to include said extracted circuits into a respective number of ASIC chips or the like, and to connect them preferably via a supervising General Controller Unit (12) to a plurality of standard and low-price processors (40), which have the task to supply the ASIC and the multiple functions thereof with enough computing power.

    Abstract translation: 本发明涉及嵌入式处理系统和电子控制单元(ECU)以及自主嵌入式计算解决方案领域。 本发明提出从系统的主处理器或控制器中移除或提取特定于应用的支持功能和相应的I / O子系统,以将所述提取的电路包括在相应数量的ASIC芯片等中,并将它们连接 优选地通过监控总控制器单元(12)到多个标准和低价格处理器(40),其具有向ASIC提供其多个功能的足够的计算能力的任务。

    TCET EXPANDER
    2.
    发明申请
    TCET EXPANDER 审中-公开
    TCET扩展器

    公开(公告)号:WO2004057431A2

    公开(公告)日:2004-07-08

    申请号:PCT/EP2003/012167

    申请日:2003-10-31

    Abstract: The present invention relates to the field of embedded processing systems and electronic control units (ECUs)and to autonomic embedded computing solutions. The present invention proposes to remove or extract the application-specific support functions and respective I/O subsystems from the main processors or controllers of the system, to include said extracted circuits into a respective number of ASIC chips or the like, and to connect them preferably via a supervising General Controller Unit (12) to a plurality of standard and low-price processors (40), which have the task to supply the ASIC and the multiple functions thereof with enough computing power.

    Abstract translation: 本发明涉及嵌入式处理系统和电子控制单元(ECU)以及自主嵌入式计算解决方案领域。 本发明提出从系统的主处理器或控制器中移除或提取特定于应用的支持功能和相应的I / O子系统,以将所述提取的电路包括在相应数量的ASIC芯片等中,并将它们连接 优选地通过监控总控制器单元(12)到多个标准和低价格处理器(40),其具有向ASIC提供其多个功能的足够的计算能力的任务。

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