公开(公告)号：WO2009114120A3

公开(公告)日：2009-11-12

申请号：PCT/US2009001506

申请日：2009-03-10

Applicant: LAM RES CORP ,  FANG TONG ,  KIM YUNSANG ,  KIM KEECHAN ,  STOJAKOVIC GEORGE

Inventor： FANG TONG ,  KIM YUNSANG ,  KIM KEECHAN ,  STOJAKOVIC GEORGE

IPC: H01L21/3065 ,  H01L21/302

CPC classification number: H01L21/67028 ,  H01J37/32642 ,  H01L21/02087 ,  H01L21/3065

Abstract: A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer extending above and below an apex of the bevel edge. A process gas is introduced into the reaction chamber and energized into a plasma. The bevel edge is cleaned with the plasma so as to remove the layer below the apex without removing all of the layer above the apex.

Abstract translation: 提供一种清洁半导体衬底的斜边缘的方法。 将半导体衬底放置在等离子体处理设备的反应室中的衬底支撑件上。 衬底具有覆盖衬底的顶表面和斜面边缘的介电层，该层在斜面边缘的顶点的上方和下方延伸。 将工艺气体引入反应室并通电为等离子体。 斜面边缘用等离子体清洁，以便除去顶点以下的层，而不会移除顶点上方的所有层。

公开(公告)号：WO2005022612A1

公开(公告)日：2005-03-10

申请号：PCT/SG2004/000265

申请日：2004-08-31

Applicant: INFINEON TECHNOLOGIES AG ,  KABUSHIKI KAISHA TOSHIBA ,  EGGER, Ulrich ,  ZHUANG, Haoren ,  STOJAKOVIC, George ,  TOMIOKA, Kazuhiro

Inventor： EGGER, Ulrich ,  ZHUANG, Haoren ,  STOJAKOVIC, George ,  TOMIOKA, Kazuhiro

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

Abstract: An Iridium barrier layer (17) is between a contact plug (13) and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode (3) and barrier layer using a fluorine-based recipe resulting in the formation of a first fence (401) clinging to the sidewalls. Next the remaining barrier layer (17) is etched using CO-based recipe. A second fence (503) is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence (401) to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition (505). The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Abstract translation: 铱阻挡层（17）在电容器的接触插塞（13）和底部电极之间。 进行蚀刻以使用氟基配方对底部电极（3）和阻挡层进行图案化，从而形成紧靠着侧壁的第一栅栏（401）。 接下来，使用基于CO的配方蚀刻剩余的阻挡层（17）。 第二围栏（503）被形成为紧固并在结构上由第一围栏支撑。 同时，基于CO的配方消除了第一围栏（401）的大部分，以去除提供给第二围栏的结构支撑。 因此，第二围栏从侧壁脱离，留下侧壁基本上没有附着的栅栏。 蚀刻的阻挡层具有侧壁过渡（505）。 侧壁在侧壁过渡之上具有相对较低的锥角，并且在侧壁过渡之下具有相对较陡的锥角。

公开(公告)号：WO2009085238A1

公开(公告)日：2009-07-09

申请号：PCT/US2008/013954

申请日：2008-12-22

Applicant: LAM RESEARCH CORPORATION ,  FANG, Tong ,  BAILEY, Andrew, D., III ,  KIM, Yunsang ,  RIGOUTAT, Olivier ,  STOJAKOVIC, George

Inventor： FANG, Tong ,  BAILEY, Andrew, D., III ,  KIM, Yunsang ,  RIGOUTAT, Olivier ,  STOJAKOVIC, George

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32366 ,  H01L21/02068 ,  H01L21/02087 ,  H01L21/32136 ,  H01L21/6708

Abstract: A method of bevel edge etching a semiconductor substrate having exposed copper surfaces with a fluorine-containing plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the fluorine-containing plasma in the bevel etcher; evacuating the bevel etcher after the bevel edge etching is completed; flowing defluorinating gas into the bevel etcher; energizing the defluorinating gas into a defluorination plasma at a periphery of the semiconductor substrate; and processing the semiconductor substrate with the defluorination plasma under conditions to prevent discoloration of the exposed copper surfaces of the semiconductor substrate upon exposure, the discoloration occurring upon prolonged exposure to air.

Abstract translation: 在半导体衬底支撑在半导体衬底支撑体上的斜面蚀刻器中，使用具有含氟等离子体的具有暴露的铜表面的半导体衬底进行斜边蚀刻的方法包括：在半导体衬底支撑体中的含氟等离子体 斜角蚀刻机 在斜边蚀刻完成之后排空斜面蚀刻机; 将脱氟气体流入斜面蚀刻机; 在所述半导体衬底的外围将所述脱氟气体通电为脱氟等离子体; 并且在曝光时防止半导体衬底的暴露的铜表面的变色的条件下，用脱氟等离子体处理半导体衬底，在长时间暴露于空气时发生变色。

公开(公告)号：WO2006011996A3

公开(公告)日：2007-04-19

申请号：PCT/US2005021047

申请日：2005-06-14

Applicant: LAM RES CORP ,  ADAMS YOKO YAMAGUCHI ,  STOJAKOVIC GEORGE ,  MILLER ALAN

Inventor： ADAMS YOKO YAMAGUCHI ,  STOJAKOVIC GEORGE ,  MILLER ALAN

IPC: C03C25/68 ,  C23F1/00

CPC classification number: H01J37/32862 ,  H01J37/32082 ,  H01L21/3065

Abstract: In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma procesing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.

Abstract translation: 在包括等离子体处理室的等离子体处理系统中，描述了优化衬底材料的耐蚀刻性的方法。 该方法包括将预涂气体混合物流入等离子体处理室，其中预涂气体混合物对蚀刻剂气流混合物具有亲和性; 从预涂气体混合物中冲出第一个等离子体; 以及引入包括所述基板材料的基板。 该方法还包括使蚀刻剂气体混合物流入等离子体处理室; 从蚀刻剂气体混合物中冲击第二个等离子体; 并用第二等离子体蚀刻衬底。 其中第一等离子体在等离子体处理室中的一组暴露表面上产生预涂层残留物，并且保持基材材料的耐蚀刻性。

公开(公告)号：WO2009114120A2

公开(公告)日：2009-09-17

申请号：PCT/US2009/001506

申请日：2009-03-10

Applicant: LAM RESEARCH CORPORATION ,  FANG, Tong ,  KIM, Yunsang ,  KIM, Keechan ,  STOJAKOVIC, George

Inventor： FANG, Tong ,  KIM, Yunsang ,  KIM, Keechan ,  STOJAKOVIC, George

IPC: H01L21/3065 ,  H01L21/30

CPC classification number: H01L21/67028 ,  H01J37/32642 ,  H01L21/02087 ,  H01L21/3065

Abstract: A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer extending above and below an apex of the bevel edge. A process gas is introduced into the reaction chamber and energized into a plasma. The bevel edge is cleaned with the plasma so as to remove the layer below the apex without removing all of the layer above the apex.

Abstract translation: 提供了一种清洁半导体衬底的斜面边缘的方法。 将半导体衬底放置在等离子体处理设备的反应室中的衬底支撑件上。 衬底具有覆盖衬底的顶面和斜面边缘的介电层，所述层在斜面边缘的顶点上方和下方延伸。 处理气体被引入反应室并激发成等离子体。 斜面边缘用等离子体清洁以除去顶点下方的层，而不移除顶点上方的所有层。

公开(公告)号：WO2006011996A2

公开(公告)日：2006-02-02

申请号：PCT/US2005/021047

申请日：2005-06-14

Applicant: LAM RESEARCH CORPORATION ,  ADAMS, Yoko, Yamaguchi ,  STOJAKOVIC, George ,  MILLER, Alan

Inventor： ADAMS, Yoko, Yamaguchi ,  STOJAKOVIC, George ,  MILLER, Alan

IPC: B44C1/22 ,  H01L21/311

CPC classification number: H01J37/32862 ,  H01J37/32082 ,  H01L21/3065

Abstract: In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma procesing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.

Abstract translation: 在包括等离子体处理室的等离子体处理系统中，描述了优化衬底材料的耐蚀刻性的方法。 该方法包括将预涂气体混合物流入等离子体处理室，其中预涂层气体混合物对蚀刻剂气体流动混合物具有亲和力; 从预涂气体混合物中冲出第一个等离子体; 以及引入包括所述基板材料的基板。 该方法还包括将蚀刻剂气体混合物流入等离子体处理室; 从蚀刻剂气体混合物中冲击第二个等离子体; 并用第二等离子体蚀刻衬底。 其中第一等离子体在等离子体处理室中的一组暴露表面上产生预涂层残留物，并且保持基板材料的耐蚀刻性。