公开(公告)号：WO2006052738A3

公开(公告)日：2007-10-11

申请号：PCT/US2005039980

申请日：2005-11-04

Applicant: FABBRIX INC ,  PILEGGI LARRY ,  STROJWAS ANDRZEJ ,  LANZA LUCIO

Inventor： PILEGGI LARRY ,  STROJWAS ANDRZEJ ,  LANZA LUCIO

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Abstract translation: 本发明提供了一种基于使用以下结果的设计集成电路的方法和过程：1）特定的硅测试结构特征集合，以及2）将逻辑分解成简单逻辑基元的组合，从该逻辑块 是可以组装成可制造的按构造设计的。 逻辑的这种实现与用于实现集成电路上的存储器块和其他部件的光刻设置兼容，特别是通过实现几何一致的组件特征。 本发明提供了将由逻辑和存储块组成的设计重新编译到新的几何结构上以实现一组技术特定设计变化的能力，而不需要整个集成电路的完全重新设计。

公开(公告)号：WO2006052738A2

公开(公告)日：2006-05-18

申请号：PCT/US2005/039980

申请日：2005-11-04

Applicant: FABBRIX, INC. ,  PILEGGI, Larry ,  STROJWAS, Andrzej ,  LANZA, Lucio

Inventor： PILEGGI, Larry ,  STROJWAS, Andrzej ,  LANZA, Lucio

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Abstract translation: 本发明提供了一种基于使用以下结果的设计集成电路的方法和过程：1）特定的硅测试结构特征集合，以及2）将逻辑分解成简单逻辑基元的组合，从该逻辑块 是可以组装成可制造的按构造设计的。 逻辑的这种实现与用于实现集成电路上的存储器块和其它组件的光刻设置兼容，特别是通过实现几何一致的组件特征。 本发明提供了将包括逻辑和存储器块的设计重新编译到新的几何结构上以实现一组技术特定设计变化的能力，而不需要整个集成电路的完全重新设计。

公开(公告)号：WO2005036422A1

公开(公告)日：2005-04-21

申请号：PCT/US2003/029758

申请日：2003-09-16

Applicant: PDF SOLUTIONS, INC. ,  GUARDIANI, Carlo ,  DRAGONE, Nicola ,  KIBARIAN, John ,  MALAVASI, Enrico ,  RADOJCIC, Ratibor ,  STROJWAS, Andrzej

Inventor： GUARDIANI, Carlo ,  DRAGONE, Nicola ,  KIBARIAN, John ,  MALAVASI, Enrico ,  RADOJCIC, Ratibor ,  STROJWAS, Andrzej

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: Library design elements (102) are analyzed for manifacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a library are obtained. Manufacturability attributes (104) of the library design elements are determined for the particular manufacturing process, where manufacturability attributes include yield-related attributes. Library views (106) with manufacturability attributes for the library design elements are then generated, which are utilizing by an electronic design automation (EDA) tool.

Abstract translation: 对图书馆设计元素（102）进行分析，以便在使用特定制造工艺制造的IC芯片的设计中使用的可实现性。 获取图书馆的图书馆设计元素。 确定库设计元素的可制造性属性（104），用于特定制造过程，其中可制造性属性包括屈服相关属性。 然后生成具有库设计元素的可制造性属性的库视图（106），其由电子设计自动化（EDA）工具利用。