公开(公告)号：WO2012040531A3

公开(公告)日：2012-03-29

申请号：PCT/US2011/052875

申请日：2011-09-23

Applicant: INTEL CORPORATION ,  COMBS, Jonathan D. ,  SUBRAMANIAM, Kameswar ,  BRANDT, Jason

Inventor： COMBS, Jonathan D. ,  SUBRAMANIAM, Kameswar ,  BRANDT, Jason

IPC: G06F9/30 ,  G06F9/305 ,  G06F9/06

Abstract: An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.

公开(公告)号：WO2012040531A2

公开(公告)日：2012-03-29

申请号：PCT/US2011052875

申请日：2011-09-23

Applicant: INTEL CORP ,  COMBS JONATHAN D ,  SUBRAMANIAM KAMESWAR ,  BRANDT JASON

Inventor： COMBS JONATHAN D ,  SUBRAMANIAM KAMESWAR ,  BRANDT JASON

IPC: G06F9/30 ,  G06F9/06 ,  G06F9/305

CPC classification number: G06F9/384 ,  G06F9/226 ,  G06F9/26 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/4425

Abstract: An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.

Abstract translation: 一个方面的装置包括多个微码别名位置和微码存储器。 微代码子程序的微指令存储在微代码存储器中。 微指令具有微代码位置的指示。 微代码子程序的微码调用者也存储在微代码存储器中。 微代码调用者可操作地指定由微代码子程序的微指令指示的微代码别名位置中的参数的位置。 该装置还包括与微码别名位置耦合的参数位置确定逻辑。 参数位置确定逻辑可操作以响应微代码子程序的微指令，从微指令接收微代码别名位置的指示，并确定由微指令指示的微码别名位置中指定的参数的位置。

公开(公告)号：WO2012040708A3

公开(公告)日：2012-07-05

申请号：PCT/US2011053266

申请日：2011-09-26

Applicant: INTEL CORP ,  PHILLIPS JAMES E ,  SUBRAMANIAM KAMESWAR

Inventor： PHILLIPS JAMES E ,  SUBRAMANIAM KAMESWAR

IPC: G06F9/46 ,  G06F9/06 ,  G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30087 ,  G06F9/3842 ,  G06F9/3857

Abstract: An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Abstract translation: 一种包括执行逻辑的装置，包括执行指令的电路以及与执行逻辑耦合的指令执行调度器逻辑。 指令执行调度器逻辑是在提交状态更新指令下接收执行。 指令执行调度器逻辑在提交状态更新逻辑中包括等待在提交状态更新指令执行的执行直到执行提交状态更新指令为下一个提交指令。 还公开了其它装置，方法和系统。

公开(公告)号：WO2012040708A2

公开(公告)日：2012-03-29

申请号：PCT/US2011/053266

申请日：2011-09-26

Applicant: INTEL CORPORATION ,  PHILLIPS, James E. ,  SUBRAMANIAM, Kameswar

Inventor： PHILLIPS, James E. ,  SUBRAMANIAM, Kameswar

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/305 ,  G06F9/06

CPC classification number: G06F9/30087 ,  G06F9/3842 ,  G06F9/3857

Abstract: An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Abstract translation: 包括执行逻辑的装置，所述执行逻辑包括执行指令的电路以及与执行逻辑耦合的指令执行调度器逻辑。 指令执行调度器逻辑将在提交状态更新指令处接收执行。 指令执行调度器逻辑在提交状态更新逻辑处包括将等待调度执行状态更新指令处的执行以用于执行直到提交状态更新指令处的执行是下一个提交指令为止。 其他装置，方法和系统也被公开。