公开(公告)号：WO2011113661A3

公开(公告)日：2011-11-17

申请号：PCT/EP2011052431

申请日：2011-02-18

Applicant: IBM ,  IBM UK ,  SHEDIVY DAVID ALAN ,  HILLIER III PHILIP ROGERS ,  VALK KENNETH MICHAEL ,  FLYNN WILLIAM THOMAS

Inventor： SHEDIVY DAVID ALAN ,  HILLIER III PHILIP ROGERS ,  VALK KENNETH MICHAEL ,  FLYNN WILLIAM THOMAS

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F2213/0026

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

Abstract translation: 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。

公开(公告)号：WO2011113661A2

公开(公告)日：2011-09-22

申请号：PCT/EP2011/052431

申请日：2011-02-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  SHEDIVY, David, Alan ,  HILLIER III, Philip, Rogers ,  VALK, Kenneth, Michael ,  FLYNN, William, Thomas

Inventor： SHEDIVY, David, Alan ,  HILLIER III, Philip, Rogers ,  VALK, Kenneth, Michael ,  FLYNN, William, Thomas

IPC: G06F13/42

CPC classification number: G06F13/4022 ,  G06F2213/0026

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

Abstract translation: 一种用于在通过多个链路喷射分组的同时实现有序且可靠的分组传输的方法和电路，以及提供了一种设计结构以及主题电路所在的设计结构。 每个源互连芯片都维护一个喷雾掩模，其中包括用于每个目的芯片的多个可用链接，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包都分配了源互连芯片中的端到端（ETE）序列号，表示来自源设备的有序数据包流中的数据包位置。 目标互连芯片使用ETE序列号将接收到的喷射数据包按照正确的顺序重新排序，然后将数据包发送到目标设备。

公开(公告)号：WO2011120840A1

公开(公告)日：2011-10-06

申请号：PCT/EP2011/054329

申请日：2011-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  VALK, Kenneth, Michael ,  WALK, Bruce, Marshall

Inventor： VALK, Kenneth, Michael ,  WALK, Bruce, Marshall

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  H04L45/304

Abstract: A method and circuit for implementing control using a single path in a multiple path interconnect system, and a design structure on which the subject circuit resides are provided. Control TL messages include control information to be transferred between a respective source transport layer of a source interconnect chip and a destination transport layer of a destination interconnect chip. Each transport layer (TL) includes a TL message port identifying a port used to send and receive control TL messages for a pair of source TL and destination TL. The respective TL message port of the pair of source TL and destination TL defines the single path used for control messages.

Abstract translation: 一种用于在多路径互连系统中实现使用单个路径的控制的方法和电路，以及设置有该主题电路所在的设计结构。 控制TL消息包括要在源互连芯片的相应源传输层和目的地互连芯片的目的地传输层之间传送的控制信息。 每个传输层（TL）包括标识用于发送和接收一对源TL和目的地TL的控制TL消息的端口的TL消息端口。 源TL和目的地TL对的各个TL消息端口定义了用于控制消息的单个路径。

公开(公告)号：WO2011117088A1

公开(公告)日：2011-09-29

申请号：PCT/EP2011/053706

申请日：2011-03-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  SHEDIVY, David, Alan ,  HILLIER III, Philip, Rogers ,  VALK, Kenneth, Michael

Inventor： SHEDIVY, David, Alan ,  HILLIER III, Philip, Rogers ,  VALK, Kenneth, Michael

IPC: G06F13/40 ,  H04L12/56

CPC classification number: G06F13/4022 ,  H04L49/1523 ,  H04L49/251 ,  H04L49/252

Abstract: A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.

Abstract translation: 一种用于实现本地机架互连系统中的无头互连芯片的增强的链路带宽的方法和电路，以及提供了所述主题电路所在的设计结构。 无头互连芯片包括切断开关和存储和正向开关。 从在无头互连芯片上的输出链路上传送的传入链路接收分组。 切断开关和存储和正向开关都有选择地用于将从进入链路接收的分组移动到无头互连芯片上的输出链路。