PROCESS FOR THE PRODUCTION OF THIN WALLED CERAMIC STRUCTURES
    1.
    发明申请
    PROCESS FOR THE PRODUCTION OF THIN WALLED CERAMIC STRUCTURES 审中-公开
    生产薄壁陶瓷结构的工艺

    公开(公告)号:WO1997004958A1

    公开(公告)日:1997-02-13

    申请号:PCT/CA1996000496

    申请日:1996-07-23

    Abstract: A process is provided for the manufacture of thin walled ceramic structures, particularly conical or near conical shaped structures. The process involves a tape casting technique wherein a green tape is prepared from a colloidal suspension containing a ceramic powder, a binder system, a plasticizer and a solvent. The suspension is cast into a thin sheet and dried to form a pliable tape. The tape is cut into planar, shaped pieces. Non-planar components of the final structure are preformed from the cut planar tape pieces into predetermined three-dimensional shapes. The planar and preformed components are sequentially assembled within a die and compacted under pressure to form a green body. The green body is subjected first, to a burnout cycle to form a brown body, and then sintered to form the unitary, cohesive, thin walled ceramic structure.

    Abstract translation: 提供了一种用于制造薄壁陶瓷结构,特别是圆锥形或近圆锥形结构的方法。 该方法涉及一种胶带浇铸技术,其中生胶带由含有陶瓷粉末,粘合剂体系,增塑剂和溶剂的胶态悬浮液制备。 将悬浮液浇铸成薄片并干燥以形成柔韧的胶带。 将胶带切成平面的成形件。 最终结构的非平面部件由切割的平面带片预成形为预定的三维形状。 将平面和预成型的部件依次组装在模具中并在压力下压实以形成生坯体。 首先将生坯体进行烧制循环以形成棕色体,然后烧结以形成一体的,内聚的薄壁陶瓷结构体。

    A CONNECTIVE MEDIUM AND A PROCESS FOR CONNECTING ELECTRICAL DEVICES TO CIRCUIT BOARDS
    2.
    发明申请
    A CONNECTIVE MEDIUM AND A PROCESS FOR CONNECTING ELECTRICAL DEVICES TO CIRCUIT BOARDS 审中-公开
    一种将电气设备连接到电路板的连接介质和工艺

    公开(公告)号:WO1996037089A1

    公开(公告)日:1996-11-21

    申请号:PCT/CA1996000323

    申请日:1996-05-17

    Abstract: A connective medium for use in ball grid arrays for connecting electronic devices to circuit boards comprising high melting point solder alloy spheres (32) coated, by electroplating, with an outer concentric layer of a lower melting point solder alloy (34) of uniform thickness. In a further aspect, a leach barrier (30) is coated on the high melting point solder alloy (32) prior to electroplating the low melting point solder alloy (34) thereto. The leach barrier (30) forms a barrier to prevent the lead from leaching from the high melting point lead solder spheres (32) into the low melting point solder alloy (34) during the reflow heat treatment in the mounting process.

    Abstract translation: 一种用于球栅阵列的连接介质,用于将电子设备连接到电路板,其包括通过电镀涂覆有均匀厚度的较低熔点焊料合金(34)的外部同心层的高熔点焊料合金球体(32)。 在另一方面,在将低熔点焊料合金(34)电镀之前,将浸出屏障(30)涂覆在高熔点焊料合金(32)上。 浸出屏障(30)在安装过程中的回流热处理期间形成阻挡层以防止铅从高熔点铅焊料球(32)浸入低熔点焊料合金(34)中。

    ANTI-MICROBIAL COATINGS HAVING INDICATOR PROPERTIES AND WOUND DRESSINGS

    公开(公告)号:CA2284096A1

    公开(公告)日:1998-09-24

    申请号:CA2284096

    申请日:1998-02-17

    Abstract: Multilayer anti-microbial materials formed to produce an interference colour, and thus an indicator of anti-microbial effect, are provided. The materials include a partly reflective base layer and a partly reflective, partly transmissive top layer balanced to produce an interference colour. The top layer is formed from an anti-microbial metal with atomic disorder. Dissolution or a change in composition of the top layer on contacting an alcohol or electrolyte causes a change in optical path length so as to produce a change in the interference colour of the material. Multilayer, laminated wound dressings are also provided. The dressing includes a first and second layer, and preferably a third layer. The first and third layers are formed of perforated, non-adherent materials and most preferably carry an anti-microbial coating as above. The second layer is sandwiched between the first and third layers and is formed of an absorbent material. At least one of the layers is formed from a plastic material. The layers are laminated together by ultrasonic welds spaced intermittently on the dressing to allow the dressing to be cut to size with delaminating.

    7.
    发明专利
    未知

    公开(公告)号:DE69313632T2

    公开(公告)日:1998-03-26

    申请号:DE69313632

    申请日:1993-05-06

    Abstract: An electroluminescent laminate is provided that comprises: a planar phosphor layer (22); a front and a rear planar electrode (14,24) on either side of the phosphor layer; a planar dielectric layer, which is preferably composed of a thick layer (18) and a thin layer (20), between the rear electrode and the phosphor layer, the dielectric layer being formed from sintered ceramic material such that the dielectric layer provides a dielectric strength S which is greater than about 1.0 X 106 V/m and a dielectric constant such that the ratio of the dielectric constant of the dielectric layer to that of the phosphor layer is greater than about 50:1, the dielectric layer having a thickness sufficient to prevent dielectric breakdown during operation as determined by the equation d2 = V/S, wherein d2 is the thickness of the dielectric layer and V is the maximum applied voltage, the dielectric layer forming a surface adjacent the phosphor layer which is sufficiently smooth that the phosphor layer illuminates generally uniformly at a given excitation voltage, and wherein the dielectric layer is either in contact with the phosphor layer or spaced apart from it by at least one additional layer that is itself in contact with the phosphor layer and wherein the layer that is in contact with the phosphor layer is compatible with the phosphor layer.

    10.
    发明专利
    未知

    公开(公告)号:ES2109490T3

    公开(公告)日:1998-01-16

    申请号:ES93909709

    申请日:1993-05-06

    Abstract: An electroluminescent laminate is provided that comprises: a planar phosphor layer (22); a front and a rear planar electrode (14,24) on either side of the phosphor layer; a planar dielectric layer, which is preferably composed of a thick layer (18) and a thin layer (20), between the rear electrode and the phosphor layer, the dielectric layer being formed from sintered ceramic material such that the dielectric layer provides a dielectric strength S which is greater than about 1.0 X 106 V/m and a dielectric constant such that the ratio of the dielectric constant of the dielectric layer to that of the phosphor layer is greater than about 50:1, the dielectric layer having a thickness sufficient to prevent dielectric breakdown during operation as determined by the equation d2 = V/S, wherein d2 is the thickness of the dielectric layer and V is the maximum applied voltage, the dielectric layer forming a surface adjacent the phosphor layer which is sufficiently smooth that the phosphor layer illuminates generally uniformly at a given excitation voltage, and wherein the dielectric layer is either in contact with the phosphor layer or spaced apart from it by at least one additional layer that is itself in contact with the phosphor layer and wherein the layer that is in contact with the phosphor layer is compatible with the phosphor layer.

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