公开(公告)号：KR100884098B1

公开(公告)日：2009-02-19

申请号：KR1020070098163

申请日：2007-09-28

Applicant: 고려대학교 산학협력단 ,  뮤텔테크놀러지 주식회사

Inventor： 한영선 ,  피터할리만 ,  김선욱 ,  민병권

IPC: H04L27/26 ,  H04J11/00

CPC classification number: H03M13/2792 ,  H03M13/2703 ,  H03M13/655 ,  H04B1/7176 ,  H04L1/0071 ,  H04L27/2602

Abstract: An apparatus and a method for block interleaving using a mixed radix system in an MB(Multi Band)-OFDM(Orthogonal Frequency Division Multiplexing) are provided to reduce power consumption, complexity, and time delay in an interleaving process and to comprise each cell of an array processor as a simple logic of two one-bit storage space and a switch by implementing an array processor structure. In a multi band orthogonal frequency division multiplexing communication system, an interleaving device(100) block-interleaves an input stream of M bit to be transmitted by a modular k. The interleaving device includes an array processor. The array processor has M cells composed of the array with k columns and an M/k rows. The array processor inputs the input stream from a right lower cell to a final cell of a left upper cell of the array processor in a horizontal direction. After a first bit of the input stream reaches the final cell, the output of the array processor is changed from the horizontal direction to the vertical direction and the interleaved output stream is generated.

Abstract translation: 提供了使用MB（多频带）-OFDM（正交频分复用）中的混合基数的块交织的装置和方法，以减少交织过程中的功耗，复杂度和时间延迟，并且包括 作为两个1位存储空间的简单逻辑的阵列处理器和通过实现阵列处理器结构的交换机。 在多频带正交频分复用通信系统中，交织装置（100）对通过模块化k发送的M比特的输入流进行块交织。 交织装置包括阵列处理器。 阵列处理器具有由具有k列和M / k行的阵列组成的M个单元。 阵列处理器在水平方向上将输入流从右下单元输入到阵列处理器的左上单元的最后单元。 在输入流的第一位到达最终单元之后，阵列处理器的输出从水平方向改变到垂直方向，并且产生交织的输出流。