公开(公告)号：KR1020030071039A

公开(公告)日：2003-09-03

申请号：KR1020020010558

申请日：2002-02-27

Applicant: 국방과학연구소

Inventor： 윤기천 ,  박석희

IPC: G06F13/00

Abstract: PURPOSE: A data communication system is provided to eliminate a load generated at a processor of a system controller by using a clock signal, which is used for a synchronization at a control instructor, as an operating signal, and to speedily check a wrong operation or an abnormal state. CONSTITUTION: The system comprises an interface logic circuit(21), the first shift register(25), the second shift register(27), and a counter(23). The interface logic circuit(21) includes a PPD(Pulse Position Data) terminal which converts a serial control signal and a parallel state signal, and transmits or receives the converted signals, and also includes a clock terminal which receives a clock signal. The first shift register(25) converts a parallel state signal into a serial state signal, and the second register(27) converts a serial control signal into a parallel state signal. The counter(23) counts a communication frequency of the control signal and the state signal.

Abstract translation: 目的：提供数据通信系统，通过使用用于控制指导员的同步的时钟信号作为操作信号来消除在系统控制器的处理器处产生的负载，并且快速地检查错误的操作或 异常状态。 构成：该系统包括接口逻辑电路（21），第一移位寄存器（25），第二移位寄存器（27）和计数器（23）。 接口逻辑电路（21）包括转换串行控制信号和并行状态信号的PPD（脉冲位置数据）端子，并且发送或接收转换后的信号，并且还包括接收时钟信号的时钟端子。 第一移位寄存器（25）将并行状态信号转换为串行状态信号，第二寄存器（27）将串行控制信号转换成并行状态信号。 计数器（23）对控制信号和状态信号的通信频率进行计数。