公开(公告)号：KR1020100103434A

公开(公告)日：2010-09-27

申请号：KR1020100022724

申请日：2010-03-15

Applicant: 니바록스-파 에스.에이.

Inventor： 쿠신,피에르 ,  골피에르,클레어 ,  티에보드,장-필러프

IPC: C25D1/12 ,  H01L21/302 ,  H01L21/3065

CPC classification number: C25D1/10 ,  B81B2201/035 ,  B81C99/009 ,  C25D17/00

Abstract: PURPOSE: A mold for an electric fabrication and a method for manufacturing thereof are provided to reduce peeling phenomenon at a bonding layer of a conductive layer using silicon. CONSTITUTION: A mold for an electric fabrication includes next steps. A substrate is supplied. An upper layer(21') of substrate is etched to one or more patterns to an intermediate layer(22') in order to one or more cavity on a mold. The upper portion of substrate is coated with electrically insulating coating. Coating and intermediate layer is formed on a vertical wall(31') by directionally etching. The substrate has an upper layer(21') and a sub-layer(23').

Abstract translation: 目的：提供一种用于电制造的模具及其制造方法，以减少使用硅的导电层的接合层处的剥离现象。 构成：用于电气制造的模具包括下一步骤。 提供基板。 将衬底的上层（21'）蚀刻到一个或多个图案到中间层（22'），以便模具上的一个或多个腔体。 衬底的上部涂覆有电绝缘涂层。 通过定向蚀刻在垂直壁（31'）上形成涂层和中间层。 衬底具有上层（21'）和子层（23'）。

公开(公告)号：KR1020100103433A

公开(公告)日：2010-09-27

申请号：KR1020100022723

申请日：2010-03-15

Applicant: 니바록스-파 에스.에이.

Inventor： 쿠신,피에르 ,  골피에르,클레어 ,  티에보드,장-필러프

IPC: C25D1/10 ,  C23F1/02

CPC classification number: C25D1/10 ,  B29C33/3842 ,  B81C99/009 ,  B81C2201/034

Abstract: PURPOSE: A mold for an electric fabrication and a method for manufacturing thereof are provided to perform electrolysis evaporation on a concave part after at least one cavity is charged. CONSTITUTION: A mold for an electric fabrication includes next steps. An electrical conductibility layer is evaporated on a top part(20) and a lower part(22) of a wafer(21) consisting of a silicon based material. The wafer is fixed on a substrate(23) using a bonding layer. One part of the conductive layer is eliminated on the top part of the wafer. The wafer is etched to the conductivity and one or more cavity is formed within the mold. A part(27) is formed for forming a second level on the conductive layer on the top of wafer.

Abstract translation: 目的：提供一种用于电制造的模具及其制造方法，用于在至少一个空腔充电之后对凹部进行电解蒸发。 构成：用于电气制造的模具包括下一步骤。 导电层在由硅基材料构成的晶片（21）的顶部（20）和下部（22）上蒸发。 使用接合层将晶片固定在基板（23）上。 导电层的一部分在晶片的顶部被去除。 将晶片蚀刻成导电性，并在模具内形成一个或多个空腔。 形成用于在晶片顶部的导电层上形成第二电平的部分（27）。