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公开(公告)号：KR101387208B1
公开(公告)日：2014-04-29
申请号：KR1020120059915
申请日：2012-06-04
Applicant: 삼성전기주식회사
Abstract: 본 발명은 임베디드 기판 제조방법 및 임베디드 기판에 관한 것이다. 본 발명의 하나의 실시예에 따라, 일면에서 수평방향으로 돌출된 캐비티 지지부를 갖도록 소자를 몰딩하여 모듈을 형성하는 단계; 캐비티를 갖는 코어기판을 준비하는 단계; 캐비티 지지부에 의해 지지되도록 코어기판의 캐비티에 몰딩된 모듈을 실장하는 단계; 및 모듈이 실장된 코어기판의 상하부 양쪽에서 제1 및 제2 절연체로 일괄 적층하여 임베디드 기판을 형성하는 단계; 를 포함하는 임베디드 기판 제조방법이 제안된다. 또한, 그에 따라 제조되는 임베디드 기판이 제안된다.
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公开(公告)号：KR101097524B1
公开(公告)日：2011-12-22
申请号：KR1020100087124
申请日：2010-09-06
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A method for manufacturing a multi-layer circuit board is provided to make the vertical and horizontal contraction rates of a board the same during a compression process. CONSTITUTION: The amount of deformation of a board is predicted before compression(S602). The thickness of each area of a metal plate is set by the predicted amount of deformation of the board(S604). A via hole is formed by scale control in consideration of the predicted amount of deformation of the board(S606). A press device receives laminated boards. The boards are compressed by metal plates under high temperature and pressure(S608).
Abstract translation: 目的：提供一种制造多层电路板的方法，以在压缩过程中使板的垂直和水平收缩率相同。 构成：压缩前预测板的变形量（S602）。 金属板的每个区域的厚度由预测的板的变形量设定（S604）。 考虑到预测的板的变形量，通过刻度控制形成通孔（S606）。 压制装置接收层压板。 板在高温高压下被金属板压制（S608）。
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公开(公告)号：KR1020100042387A
公开(公告)日：2010-04-26
申请号：KR1020080101522
申请日：2008-10-16
Applicant: 삼성전기주식회사
IPC: H05K3/18
CPC classification number: H05K3/18 , C23C18/1683 , H05K2203/072
Abstract: PURPOSE: A PCB and a manufacturing method thereof are provided to prevent the deformation of a PCB without using a separate member by forming a grain of a circuit pattern as a small size. CONSTITUTION: A first electrode is formed in an area except deformation vulnerable area by electroless plating(S110). A second electrode is formed in the deformation vulnerable area by the electroless plating(S120). A first circuit pattern is formed by executing a first electro plating using the first electrode(S130). A second circuit pattern is formed by executing a second electro plating using the second electrode in order to have a smaller grain size than the grain size of the first circuit pattern(S140). The electric current density of the second electro plating is smaller than the electric current density of the first electro plating.
Abstract translation: 目的：提供一种PCB及其制造方法，以通过形成小尺寸的电路图案的颗粒来防止PCB的变形而不使用单独的构件。 构成：第一电极通过无电镀形成在除易变形区域以外的区域（S110）。 第二电极通过化学镀形成在变形脆弱区域（S120）中。 通过使用第一电极执行第一电镀形成第一电路图案（S130）。 通过使用第二电极执行第二电镀形成第二电路图案，以便具有比第一电路图案的晶粒尺寸更小的晶粒尺寸（S140）。 第二电镀的电流密度小于第一电镀的电流密度。
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公开(公告)号：KR1020090131058A
公开(公告)日：2009-12-28
申请号：KR1020080056837
申请日：2008-06-17
Applicant: 삼성전기주식회사
CPC classification number: H05K1/14 , H01L23/147 , H05K1/0271
Abstract: PURPOSE: A PCB for a semiconductor package and a manufacturing method thereof are provided to make size of grains of metal layers smaller than size of a solder surface, thereby effectively solving a bending problem. CONSTITUTION: Component sides for mounting a semiconductor are included in each one side of bare PCBs(101,201). Solder sides for coupling with external components are included in the other sides of the bare substrates. First circuit metal layers(102,202) are formed on the component sides. Second circuit metal layers are formed on the solder sides. An average size ratio between grains which constitute the first metal layers and grains which constitute the second metal layers is 1:5 to 1:15.
Abstract translation: 目的：提供一种用于半导体封装的PCB及其制造方法，以使金属层的颗粒尺寸小于焊料表面的尺寸，从而有效地解决弯曲问题。 构成：用于安装半导体的组件侧包括在裸PCB（101,201）的每一侧。 用于与外部组件耦合的焊接侧包括在裸基板的另一侧。 第一电路金属层（102,202）形成在部件侧。 第二电路金属层形成在焊料侧。 构成第一金属层的晶粒和构成第二金属层的晶粒之间的平均尺寸比为1:5〜1:15。
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公开(公告)号：KR1020090047317A
公开(公告)日：2009-05-12
申请号：KR1020070113417
申请日：2007-11-07
Applicant: 삼성전기주식회사
IPC: H05K3/18
CPC classification number: H05K3/14 , H05K1/0271 , H05K3/188
Abstract: 인쇄회로기판 회로형성방법이 개시된다. 변형이 예측되는 변형취약영역을 갖는 기판에 회로를 형성하는 방법으로서, 기판에 도전성 물질을 증착하여 시드층을 형성하는 단계, 시드층에 감광성 필름을 적층하는 단계, 회로가 형성될 위치에 상응하여 감광성 필름의 일부를 선택적으로 제거하는 단계 및 상기 변형취약영역에 도금입자가 크게 형성되도록 시드층을 전극으로 전해질 용액에서 전해 도금하는 단계를 포함하는 인쇄회로기판 제조방법은, 인쇄회로기판의 변형취약영역에 도금입자의 크기를 크게 함으로써, 부분별로 기계적 강성이 조절되어 별도의 자재를 추가로 삽입하지 않고도 기판의 변형을 방지할 수 있고 박형 기판을 제조할 수 있다.
도금입자, 변형, 도금-
Patent Agency Ranking
公开(公告)号：KR101376950B1
公开(公告)日：2014-03-20
申请号：KR1020120157174
申请日：2012-12-28
Applicant: 삼성전기주식회사
IPC: H05K3/46
Abstract: The present invention relates to a double plate for pressing substrates and a method for pressing substrates. According to one embodiment of the present invention, provided is a double plate which is interposed between substrates when multiple substrates are pressed and comprises: a first plate: a second plate having different coefficient of thermal expansion from the first plate; and a bonding layer arranged between the first and the second plates, bonding the plates and curtailing mutual influence due to the thermal expansion of each plate. Also, a method for pressing substrates using the double plate is provided.
Abstract translation: 本发明涉及一种用于压制基板的双板和一种用于压制基板的方法。 根据本发明的一个实施例，提供了当压制多个基板时介于基板之间的双板，并且包括：第一板：具有与第一板不同的热膨胀系数的第二板; 以及布置在第一和第二板之间的接合层，由于每个板的热膨胀而粘合板并减少相互影响。 此外，提供了使用双板压制基板的方法。
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公开(公告)号：KR1020130015718A
公开(公告)日：2013-02-14
申请号：KR1020110077878
申请日：2011-08-04
Applicant: 삼성전기주식회사
CPC classification number: C25D17/06 , C25D17/10 , H01L21/687
Abstract: PURPOSE: A jig for plating and a plating apparatus using the same are provided to improve plating accuracy by reducing the plating deviation of a substrate in order to reduce plating defection rate, thereby decreasing material and processing costs for the plating. CONSTITUTION: A jig for plating includes a plating bath(150), a plating jig(120), an anode(140), a position controlling member(130), and a flow pipe(170). The plating bath is filled with a plating solution. The plating jig fixes substrate(110). The anode is placed to be parallel to the substrate. One end of the position controlling substrate is connected to the plating jig, and the other is connected to the anode in order to fix the substrate and the anode. The position controlling substrate controls a distance between the substrate and the anode. Plural holes are formed on the front side of the anode. A hole through which a plating solution passes is formed at the position controlling substrate. The flow pipe runs the plating solution.
Abstract translation: 目的：提供电镀用夹具和使用该夹具的电镀装置，以通过降低基板的电镀偏差来提高电镀精度，以减少电镀缺陷率，从而降低镀层的材料和加工成本。 构成：用于电镀的夹具包括镀浴（150），电镀夹具（120），阳极（140），位置控制构件（130）和流量管（170）。 电镀液中填充有镀液。 电镀夹具固定基板（110）。 将阳极放置成平行于衬底。 位置控制基板的一端连接到电镀夹具，另一端连接到阳极，以固定基板和阳极。 位置控制基板控制基板和阳极之间的距离。 在阳极的正面形成有多个孔。 在位置控制基板上形成电镀液通过的孔。 流动管道运行电镀液。
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公开(公告)号：KR1020120123896A
公开(公告)日：2012-11-12
申请号：KR1020110041507
申请日：2011-05-02
Applicant: 삼성전기주식회사
Abstract: PURPOSE: A deflection interpretation method and apparatus of a substrate strip are provided to conspicuously shorten time to be required deflection interpretation by automatically outputting a deflection interpretation result based on extracted shape information and valid physical properties. CONSTITUTION: A shape information extraction unit(210) extracts area shape information of a substrate strip from Gerber data. A valid physical property operation unit(220) computes area valid physical properties from the ratio of solder-resist and copper foil which is computed based on the extracted shape information. A deflection interpretation performing unit(230) performs deflection interpretation of the substrate strip based on the computed area valid physical properties. The deflection interpretation performing unit converts the computed area valid physical properties into a file which is executable in a construction analysis program. A drawing unit(240) displays the area shape information which is extracted in the shape information extraction unit. [Reference numerals] (210) Shape information extraction unit; (220) Valid physical property operation unit; (230) Deflection interpretation performing unit; (240) Drawing unit; (250) Storing unit; (260) Dial log unit
Abstract translation: 目的：通过基于提取的形状信息和有效的物理特性自动输出偏转解释结果，提供了基板条的偏转解释方法和装置，以显着缩短需要偏转解释的时间。 构成：形状信息提取单元（210）从格伯数据提取衬底条的区域形状信息。 有效的物理属性操作单元（220）根据所提取的形状信息计算的阻焊层和铜箔的比例，计算面积有效的物理性质。 偏转解释执行单元（230）基于所计算的区域有效物理特性来执行衬底条的偏转解释。 偏转解释执行单元将计算出的区域有效物理属性转换为在构造分析程序中可执行的文件。 绘图单元（240）显示在形状信息提取单元中提取的区域形状信息。 （附图标记）（210）形状信息提取单元; （220）有形物理操作单元; （230）变形解释执行单元; （240）绘图单位; （250）存储单元; （260）拨号日志单元
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公开(公告)号：KR1020120018526A
公开(公告)日：2012-03-05
申请号：KR1020100081421
申请日：2010-08-23
Applicant: 삼성전기주식회사
CPC classification number: H01L2224/16225 , H01L2224/73204 , H01L2924/15159 , H01L2924/15311 , H01L24/26 , H01L23/04 , H01L23/28
Abstract: PURPOSE: A package of a semiconductor and a method of manufacturing the same are provided to prevent warapage due to the thermal expansion coefficient mismatch between a semiconductor chip and a printed circuit. CONSTITUTION: A printed circuit board(110) is formed to have at least one stepped part. A semiconductor chip(130) is mounted in the top side of the printed circuit board. A first binding member(150) is formed between the printed circuit board and a semiconductor chip. A filler part(170) is formed in order to protect the first binding member. A second binding member(190) is formed in order to unite the printed circuit board with the board.
Abstract translation: 目的：提供一种半导体封装及其制造方法，以防止半导体芯片与印刷电路之间的热膨胀系数不匹配引起的故障。 构成：印刷电路板（110）形成为具有至少一个台阶部分。 半导体芯片（130）安装在印刷电路板的顶侧。 第一装订构件（150）形成在印刷电路板和半导体芯片之间。 形成填料部分（170）以保护第一结合部件。 形成第二装订构件（190）以将印刷电路板与板组合。
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公开(公告)号：KR100965336B1
公开(公告)日：2010-06-22
申请号：KR1020080056837
申请日：2008-06-17
Applicant: 삼성전기주식회사
Abstract: 본 발명은 반도체 패키지용 인쇄회로기판 및 그 제조방법에 관한 것으로서, 베어 기판의 부품면에 형성된 회로용 제1금속층과 솔더면에 형성된 회로용 제2금속층을 구성하는 결정립의 평균 크기비가 1:5∼1:15가 되도록 함으로써 고온의 반도체 패키지 공정에서의 휨 현상을 개선하는 것을 특징으로 한다.
반도체 패키지용 인쇄회로기판, 베어 PCB, 부품면, 솔더면, 결정립 크기비
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