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公开(公告)号：KR1020090008917A
公开(公告)日：2009-01-22
申请号：KR1020070072276
申请日：2007-07-19
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/2463 , H01L21/28273 , H01L27/10885 , H01L27/10891
Abstract: A mask ROM and a method for manufacturing the same are provided to perform the coding of the mask ROM by comprising on-cell and off cell of the mask ROM according to a conductive pattern connected to a gate electrode. A plurality of gate electrodes(114) are independently formed on a semiconductor substrate. Source and drain regions are formed in both sides of the gate electrode. A bit line(132) is connected to the drain region. A conductive pattern(134) is electrically connected to a part of the plurality of gate electrodes. A word line(152) is electrically connected to the conductive pattern. The word line is arranged vertically to the bit line.
Abstract translation: 提供掩模ROM及其制造方法，通过根据连接到栅电极的导电图案，通过包括掩模ROM的接通单元和关闭单元来执行掩模ROM的编码。 在半导体衬底上独立地形成多个栅电极（114）。 源极和漏极区域形成在栅电极的两侧。 位线（132）连接到漏区。 导电图案（134）电连接到多个栅电极的一部分。 字线（152）电连接到导电图案。 字线垂直于位线排列。
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公开(公告)号：KR100723437B1
公开(公告)日：2007-05-30
申请号：KR1020060048945
申请日：2006-05-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
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公开(公告)号：KR1020050020042A
公开(公告)日：2005-03-04
申请号：KR1020030057684
申请日：2003-08-20
Applicant: 삼성전자주식회사
Inventor： 권혁기
IPC: H01L27/115
Abstract: PURPOSE: A non-volatile semiconductor device and a manufacturing method thereof are provided to maximize the efficiency of programming in spite of the application of a low voltage by changing properly the structure of a floating gate. CONSTITUTION: A non-volatile semiconductor device includes a semiconductor substrate(100) with an active region and an isolation region, a source region, a pair of floating gates, a word line and a drain region. The source region(120a) is formed within the active region. The pair of floating gates(112) are formed on the substrate of the active region. A lower portion of each floating gate is prolonged to a channel region and an edge of the lower portion is roundly formed. The word line(118) is formed on the floating gate. The drain region(120b) is partially overlapped with the word line.
Abstract translation: 目的：提供非易失性半导体器件及其制造方法，以便通过适当地改变浮动栅极的结构来尽可能地提高编程效率，尽管施加了低电压。 构成：非易失性半导体器件包括具有有源区和隔离区的半导体衬底（100），源区，一对浮置栅，字线和漏区。 源区域（120a）形成在有源区域内。 一对浮栅（112）形成在有源区的基板上。 每个浮动栅极的下部延伸到沟道区域，并且下部的边缘被圆形地形成。 字线（118）形成在浮动栅极上。 漏极区域（120b）与字线部分重叠。
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公开(公告)号：KR100753153B1
公开(公告)日：2007-08-30
申请号：KR1020060008419
申请日：2006-01-26
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/42336 , H01L27/115 , H01L27/11521 , H01L29/7881
Abstract: 비휘발성 기억 장치 및 그 제조 방법을 제공한다. 이 장치는 반도체 기판에 정의된 활성영역과, 게이트 절연막을 개재하여 상기 활성영역의 상부를 가로지르는 제어 게이트 전극을 포함한다. 상기 활성영역에 부유 게이트가 형성되어 상기 제어 게이트 전극을 관통하며 상기 반도체 기판 내에 소정 깊이 신장된다. 상기 제어게이트 전극 및 상기 부유 게이트 사이와, 상기 반도체 기판 및 상기 부유 게이트 사이에 연속적으로 터널 절연막이 개재된다. 상기 부유 게이트는 상기 제어게이트 전극을 구성하는 도전막 및 상기 기판을 연속적으로 식각하여 트렌치를 형성하고, 상기 트렌치 및 상기 도전막의 측벽에 터널절연막을 형성한 후 형성할 수 있다. 상기 부유 게이트는 상기 트렌치 내에 형성됨으로써 상기 기판의 소정 깊이까지 신장된다.
비휘발성, 트렌치, 펀치쓰루-
公开(公告)号：KR1020070029326A
公开(公告)日：2007-03-14
申请号：KR1020050083986
申请日：2005-09-09
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: A semiconductor device and its manufacturing method are provided to prevent an INWE(Inverse Narrow Width Effect) and a punchthrough by forming a doped region at a periphery of an active region using a tilt ion implantation process. A mask pattern is formed on a substrate(110). A tilt ion implantation process is performed on the resultant structure by using the mask pattern as an ion implantation mask. A spacer(125p) is formed at sidewalls of the mask pattern. A trench(130t) is formed on the substrate by performing an etching process on the resultant structure using the mask pattern and the spacer as an etch mask. The mask pattern includes a nitride layer.
Abstract translation: 提供半导体器件及其制造方法，以通过使用倾斜离子注入工艺在活性区域的周围形成掺杂区域来防止INWE（反向窄宽度效应）和穿透。 在衬底（110）上形成掩模图案。 通过使用掩模图案作为离子注入掩模对所得结构进行倾斜离子注入工艺。 在掩模图案的侧壁处形成间隔物（125p）。 通过使用掩模图案和间隔物作为蚀刻掩模对所得结构进行蚀刻处理，在衬底上形成沟槽（130t）。 掩模图案包括氮化物层。
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Patent Agency Ranking
公开(公告)号：KR1020070010923A
公开(公告)日：2007-01-24
申请号：KR1020050065914
申请日：2005-07-20
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11524 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/66825
Abstract: An NVM(non-volatile memory) device having a 3-transistor memory cell is provided to make an interval between a cell gate pattern and a select line become smaller than the resolution limit of a photolithography process by properly adjusting the thickness of a spacer layer for forming second sacrificial spacers. A source region and a drain region(36b) are formed in a semiconductor substrate, separated from each other. A source select line(SSL) and a drain select line(DSL) is formed on the semiconductor substrate between the source region and the drain region, respectively adjacent to the source region and the drain region. A cell gate pattern is disposed between the source select line and the drain select line. A first floating impurity region is formed in the semiconductor substrate under a gap region between the source select line and the cell gate pattern. A second floating impurity region is formed in the semiconductor substrate under a gap region between the drain select line and the cell gate pattern. The interval between the cell gate pattern and the select line is smaller than that width of the select line. A floating gate(FG), an inter-gate dielectric and a wordline pattern are sequentially stacked in the cell gate pattern, and the select line is made of a single conductive layer.
Abstract translation: 提供具有3晶体管存储单元的NVM（非易失性存储器）器件，以通过适当地调整间隔层的厚度使得单元栅极图案和选择线之间的间隔变得小于光刻工艺的分辨率极限 用于形成第二牺牲隔离物。 源极区域和漏极区域（36b）形成在半导体衬底中，彼此分离。 源极选择线（SSL）和漏极选择线（DSL）形成在源极区域和漏极区域之间的半导体衬底上，分别与源极区域和漏极区域相邻。 单元栅极图案设置在源极选择线和漏极选择线之间。 在源极选择线和单元栅极图案之间的间隙区域，在半导体衬底中形成第一浮置杂质区。 在漏极选择线和单元栅极图案之间的间隙区域的半导体衬底内形成第二浮置杂质区。 单元栅极图案和选择线之间的间隔小于选择线的宽度。 浮栅（FG），栅极间电介质和字线图案依次层叠在单元栅极图案中，选择线由单个导电层制成。
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公开(公告)号：KR1020060099693A
公开(公告)日：2006-09-20
申请号：KR1020050021074
申请日：2005-03-14
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328 , H01L29/7885 , H01L29/66825
Abstract: 비휘발성 기억장치 및 그 제조방법을 제공한다. 이 소자는 기입 게이트와 소거 게이트가 부유게이트에 대향하여 형성되어 기입시 부유게이트에 커플링되는 전압을 높이고 소거시 부유게이트에 커플링되는 전압을 낮출 수 있는 구조를 가진다. 따라서, 기입 및 소거 전압을 낮출 수 있고 확산 영역에 고전압이 인가되지 않기 때문에 채널 길이를 감소하여 셀 크기를 축소할 수 있다.
비휘발성, 기입, 소거Abstract translation: 它提供了一个非易失性存储器件及其制造方法。 该装置具有能够降低在反对浮动栅极到增大写入期间耦合到所述浮栅上的电压形成写栅和擦除擦除栅期间耦合到所述浮栅上的电压的结构。 因此，为了降低写入和擦除电压，并且可以减小单元尺寸，因为它不具有高电压施加到扩散区域施加以减小沟道长度。
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公开(公告)号：KR1020160116104A
公开(公告)日：2016-10-07
申请号：KR1020150041667
申请日：2015-03-25
Applicant: 삼성전자주식회사
IPC: H01L29/423 , H01L21/76
CPC classification number: H01L29/0653 , H01L21/823871 , H01L27/0924 , H01L29/41791 , H01L29/45
Abstract: 반도체소자는, 일방향으로연장되는활성패턴들을정의하는소자분리막을포함하는기판, 상기기판상에상기활성패턴들및 상기소자분리막을가로지르는게이트전극, 및상기활성패턴들사이의상기소자분리막상에제공되고, 상기게이트전극에연결되는게이트콘택을포함한다. 상기게이트콘택은상기게이트전극의상부와접하는바디부및 상기게이트전극의일 측벽을따라상기바디부로부터상기소자분리막으로연장되는연장부를포함한다.
Abstract translation: 半导体器件包括衬底。 该半导体器件包括在该衬底上的栅电极。 半导体器件包括在栅电极上的栅极接触。 在一些实施例中，鳍状体从衬底突出，并且栅电极在鳍状体上。 此外，在一些实施例中，栅极接触部分地在栅电极中。
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公开(公告)号：KR1020080100649A
公开(公告)日：2008-11-19
申请号：KR1020070046615
申请日：2007-05-14
Applicant: 삼성전자주식회사
IPC: H01L21/3205 , H01L21/28
CPC classification number: H01L27/105 , H01L21/76898 , H01L21/8221 , H01L23/485 , H01L27/0688 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11551 , H01L2924/0002 , H01L2924/00
Abstract: The logic circuit and the memory circuit of different thickness of the gate insulating layer are formed on the different substrate. These substrates are laminated. The logic circuit and memory circuit are electrically connected through the through via. The semiconductor device(100) is provided. The semiconductor layer(101) including the first circuit having the gate insulating layer of the first thickness is formed on the first substrate(110). The second semiconductor layer(102) including second circuit having the gate insulating layer of the second thickness different from the first thickness is formed on the second substrate(150). The via(170) passes through a part of the first and the second semiconductor layer, and connects electrically the first and the second circuit.
Abstract translation: 栅极绝缘层的不同厚度的逻辑电路和存储电路形成在不同的衬底上。 层压这些基板。 逻辑电路和存储器电路通过通孔电连接。 提供半导体器件（100）。 包括具有第一厚度的栅极绝缘层的第一电路的半导体层（101）形成在第一基板（110）上。 在第二基板（150）上形成包括第二厚度不同于第一厚度的栅极绝缘层的第二电路的第二半导体层（102）。 通孔（170）穿过第一和第二半导体层的一部分，并且电连接第一和第二电路。
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公开(公告)号：KR1020080010503A
公开(公告)日：2008-01-31
申请号：KR1020060070524
申请日：2006-07-27
Applicant: 삼성전자주식회사
Inventor： 권혁기
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11521 , H01L21/76229 , H01L21/76897 , H01L27/11519
Abstract: A flash memory of a split gate type and a method of manufacturing the same are provided to improve an electrical performance by easily increasing a coupling ratio. A flash memory of a split gate type includes a trench element isolating film, an active area, a common source area(18), a floating gate(16), and a word line(20). The trench element isolating film is formed on a semiconductor substrate(10). A surface of the active area is lower than a surface of the trench element isolating film. A part of the active area adjacent to the trench element isolating film has a step shape. The common source area is positioned in a stepped part of the active area having the step shape and is formed adjacent to the trench element isolating film in a direction substantially perpendicular to the trench element isolating film. The floating gate is positioned on the common source area of the stepped part. The word line is formed on the floating gate.
Abstract translation: 提供了分闸式闪存及其制造方法，以通过容易地增加耦合比来改善电性能。 分离栅型闪速存储器包括沟槽元件隔离膜，有源区，公共源区（18），浮栅（16）和字线（20）。 沟槽元件隔离膜形成在半导体衬底（10）上。 有源区的表面低于沟槽元件隔离膜的表面。 与沟槽元件隔离膜相邻的有源区域的一部分具有台阶形状。 公共源极区域位于具有台阶形状的有源区域的阶梯部分中，并且在与沟槽元件隔离膜基本垂直的方向上与沟槽元件隔离膜相邻地形成。 浮栅位于阶梯部分的共同源极区域上。 字线形成在浮动门上。
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