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公开(公告)号：WO2022045563A1
公开(公告)日：2022-03-03
申请号：PCT/KR2021/008449
申请日：2021-07-02
Applicant: 삼성전자주식회사
Abstract: 본 발명은 판넬 및 모터가 마련된 장치에 있어서, 특정 구동 조건과 독립적으로 판넬 개방 시 모터의 동작을 중단 시키고 판넬 개방 상황을 사용자에게 알릴 수 있는 환기 장치, 회로 어셈블리 및 그 제어방법을 제공한다. 일 실시예에 따른 회로 어셈블리는 판넬이 본체에 결합되면 닫히고 상기 판넬의 적어도 일부분이 상기 본체와 분리되면 개방되는 스위치; 및 상기 스위치가 개방되면 동작이 중단되는 모터; 상기 스위치와 연결되고 상기 스위치의 개방에 대응하여 알림 신호를 출력하는 마이컴;을 포함한다.
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公开(公告)号：KR1020110031522A
公开(公告)日：2011-03-29
申请号：KR1020090088817
申请日：2009-09-21
Applicant: 삼성전자주식회사
IPC: G11C11/4078 , G11C11/408 , G11C11/4063
CPC classification number: G11C29/08 , G11C11/401
Abstract: PURPOSE: A memory device and a memory system having the same and a method of controlling the same are provided to improve an operation speed by allowing a control parameter of a plurality of sub blocks to be set respectively. CONSTITUTION: In a memory device and a memory system having the same and a method of controlling the same, a memory cell array comprises a plurality of memory cells A plurality of memory cells are divided into a plurality of memory blocks. A control setting circuit(410) maps the address of a plurality of sub blocks. The control setting circuit reconstructs the sub blocks. The control setting circuit sets the control parameter at sub blocks respectively and includes a status register(460) and an address mapping unit(470).
Abstract translation: 目的：提供具有相同的存储器件和存储器系统及其控制方法，以通过分别设置多个子块的控制参数来提高操作速度。 构成：在具有相同的存储器件和存储器系统及其控制方法中，存储单元阵列包括多个存储器单元多个存储器单元被分成多个存储块。 控制设置电路（410）映射多个子块的地址。 控制设置电路重构子块。 控制设定电路分别设置子块的控制参数，包括状态寄存器（460）和地址映射单元（470）。
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公开(公告)号：KR1020070040242A
公开(公告)日：2007-04-16
申请号：KR1020050095701
申请日：2005-10-11
Applicant: 삼성전자주식회사
Inventor： 박기원
IPC: G11C7/14 , G11C29/00 , G11C11/4099
Abstract: 본 발명은 반도체 메모리 장치를 공개한다. 에지에 배치된 에지 비트 라인들과 워드 라인들 사이에 연결된 에지 메모리 셀들 그리고 더미 비트 라인들과 워드 라인들 사이에 연결된 에지 더미 셀들을 구비하는 에지 서브 어레이 블록과 비트 라인들과 상기 워드 라인들 사이에 연결된 메모리 셀들을 구비하는 서브 어레이 블록을 구비하는 메모리 셀 어레이와, 어드레스 신호를 입력으로 받아 제1, 제2 선택 신호를 발생하는 선택 신호 발생부와, 상기 제1 선택 신호에 응답하여 상기 에지 비트 라인들과 상기 비트 라인들 사이의 전압 차를 감지하여 증폭하고 상기 제2 선택 신호에 응답하여 상기 더미 비트 라인들과 상기 비트 라인들 사이의 전압 차를 감지하여 증폭하는 센스 증폭부를 구비한다. 따라서 제1 선택 신호에 응답하여 에지 비트 라인이, 제2 선택 신호에 응답하여 더미 비트라인이 선택적으로 동작하게 하여 에지 메모리 셀과 에지 더미 셀을 메모리 셀과 같이 리드, 라이트 할 수 있도록 하며, 테스트 모드에서 에지 메모리 셀과 에지 더미 셀을 메모리 셀과 동일한 환경에서 테스트 할 수 있도록 한다.
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公开(公告)号：KR1020010066405A
公开(公告)日：2001-07-11
申请号：KR1019990068120
申请日：1999-12-31
Applicant: 삼성전자주식회사
Inventor： 박기원
IPC: H04B1/40
CPC classification number: H04M1/656 , H04M2201/36
Abstract: PURPOSE: An apparatus for recording or regenerating call contents in a portable phone is provided to record and/or regenerate call contents in a portable phone. CONSTITUTION: An A/D(Analog to Digital) converter(10) converts a subscriber's analog voice signal inputted through a mike into PCM(Pulse Code Modulation) data. A D/A(Digital to Analog) converter(20) converts the other side's voice inputted in the form of PCM data into an analog signal. A voice encoder(30) compresses the PCM data and outputs required packet data. A transceiver(40) transmits or receives radio signals through an antenna. The first memory(60) stores the subscriber's voice of the packet data form outputted from the voice encoder(30). The second memory(70) stores the other side's voice, received through the antenna, in the packet data form. A control part(50) generates various commands and control signals in order to control operations for the recording and regeneration of call contents.
Abstract translation: 目的：提供一种用于在便携式电话中记录或再生呼叫内容的装置，用于在便携式电话中记录和/或再生呼叫内容。 构成：A / D（模拟到数字）转换器（10）将通过麦克风输入的用户模拟语音信号转换为PCM（脉冲编码调制）数据。 数模转换器（20）将以PCM数据形式输入的另一侧的声音转换为模拟信号。 语音编码器（30）压缩PCM数据并输出所需的分组数据。 收发器（40）通过天线发送或接收无线电信号。 第一存储器（60）存储从语音编码器（30）输出的分组数据形式的订户的语音。 第二存储器（70）以分组数据形式存储通过天线接收的另一侧的语音。 控制部件（50）生成各种命令和控制信号，以便控制呼叫内容的记录和再生的操作。
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公开(公告)号：KR1020150043748A
公开(公告)日：2015-04-23
申请号：KR1020130122522
申请日：2013-10-15
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/0331 , H01L33/10 , H01L2933/0016 , H01L21/0274 , H01L21/31144 , H01L21/3205
Abstract: 본발명의실시형태에따른반도체소자의패턴형성방법은, 기판상에제1 마스크층및 제2 마스크층을순차적으로형성하는단계, 제2 마스크층을패터닝하여제2 마스크패턴층을형성하는단계, 제2 마스크패턴층에의해노출된제1 마스크층을식각하여, 제2 마스크패턴층과의경계로부터기판상으로폭이감소하는네거티브경사영역을가지는제1 마스크패턴층을형성하는단계, 및제1 마스크패턴층에의해노출된기판상에박막층을형성하는단계를포함한다.
Abstract translation: 根据本发明的实施例的形成半导体器件的图案的方法包括以下步骤：在衬底上依次形成第一掩模层和第二掩模层; 通过图案化第二掩模层形成第二掩模图案层; 通过蚀刻由第二掩模图案层露出的第一掩模层，形成第一掩模图案层，其具有从第二掩模图案层的边界宽度减小到基板的负倾斜区域; 以及在由第一掩模图案层暴露的衬底上形成薄膜层。
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Patent Agency Ranking
公开(公告)号：KR1020020066701A
公开(公告)日：2002-08-21
申请号：KR1020010007023
申请日：2001-02-13
Applicant: 삼성전자주식회사
Inventor： 박기원
IPC: H04B1/40
CPC classification number: H04M1/6505
Abstract: PURPOSE: A recording/reproducing apparatus for a mobile communication terminal is provided to hear voice information during a telephone conversation and transmit voice information in a telephone conversation state by composing a switch unit for being switched to an A/D converting unit. CONSTITUTION: A microphone unit(20) receives a voice signal from a user and outputs the received voice signal to an A/D converting unit(30). The A/D converting unit(30) converts the voice signal received from the microphone unit(20) into a digital signal, and outputs the converted digital signal to a digital signal processing unit(40). The digital signal processing unit(40) converts the digital signal received from the A/D converting unit(30) into voice packet data to output the converted voice packet data to a memory unit(50), and converts certain voice packet data received from the memory unit(50) into a digital signal to output the converted digital signal to a D/A converting unit(60). The memory unit(50) stores the voice data packet received from the digital signal processing unit(40), and outputs the stored voice data packet to the digital signal processing unit(40) according to the request of the user. The D/A converting unit(60) converts the digital signal received from the digital signal processing unit(40) into an analog voice signal. A speaker unit(70) outputs the voice signal inputted from the D/A converting unit(60). A switch unit(100) outputs the voice signal received from the D/A converting unit(60) to the speaker unit(70) under a standby state of a mobile communication terminal, and outputs the voice signal received from the D/A converting unit(60) to the speaker unit(70) and the A/D converting unit(30) under a telephone conversation state of the mobile communication terminal.
Abstract translation: 目的：提供一种用于移动通信终端的记录/再现装置，用于在电话通话期间听到语音信息，并通过组合切换到A / D转换单元的开关单元在电话通话状态下发送话音信息。 构成：麦克风单元（20）从用户接收语音信号并将接收到的语音信号输出到A / D转换单元（30）。 A / D转换单元（30）将从麦克风单元（20）接收的语音信号转换为数字信号，并将转换的数字信号输出到数字信号处理单元（40）。 数字信号处理单元（40）将从A / D转换单元（30）接收的数字信号转换为语音分组数据，以将转换的语音分组数据输出到存储单元（50），并将从 存储单元（50）转换成数字信号，以将转换的数字信号输出到D / A转换单元（60）。 存储单元（50）存储从数字信号处理单元（40）接收的语音数据分组，并根据用户的请求将存储的语音数据分组输出到数字信号处理单元（40）。 D / A转换单元（60）将从数字信号处理单元（40）接收的数字信号转换为模拟语音信号。 扬声器单元（70）输出从D / A转换单元（60）输入的语音信号。 开关单元（100）在移动通信终端的待机状态下将从D / A转换单元（60）接收的语音信号输出到扬声器单元（70），并输出从D / A转换器 单元（60）到移动通信终端的电话通话状态下的扬声器单元（70）和A / D转换单元（30）。
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公开(公告)号：KR1020080079559A
公开(公告)日：2008-09-01
申请号：KR1020070019931
申请日：2007-02-27
Applicant: 삼성전자주식회사
Abstract: A voltage monitoring circuit and a method for monitoring a voltage are provided to measure the variation of an internal voltage when a semiconductor memory device in a package state operates. A power supply voltage selection circuit(140) selects one power supply voltage among a plurality of power supply voltages. A signal delay circuit(120) delays an input signal as much as delay time varying according to the amplitude of the selected power supply voltage. A first switch(110) transmits the input signal to the signal delay circuit when a control signal is enabled. A second switch(130) transmits an output of the signal delay circuit to an output stage when a control signal is enabled.
Abstract translation: 提供电压监视电路和用于监测电压的方法，以便当封装状态的半导体存储器件工作时测量内部电压的变化。 电源电压选择电路（140）选择多个电源电压中的一个电源电压。 信号延迟电路（120）根据所选择的电源电压的幅度延迟输入信号的延迟时间变化。 当控制信号被使能时，第一开关（110）将输入信号发送到信号延迟电路。 当控制信号被使能时，第二开关（130）将信号延迟电路的输出发送到输出级。
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公开(公告)号：KR1020060023632A
公开(公告)日：2006-03-15
申请号：KR1020040072406
申请日：2004-09-10
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C29/12 , G11C29/12005 , G11C2029/1204 , G11C29/1201 , G11C29/18
Abstract: A memory device having an open bit line cell structure uses a wafer burn-in testing scheme and a method for testing the same. The memory device includes a sense amplifier having first and second input terminals; a bit line connected to the first input terminal of the sense amplifier and extended in a first direction; an inverted bit line connected to the second input terminal of the sense amplifier and extended in a second direction; and a voltage supply means for applying the same voltage to the bit line and the inverted bit line in a precharge operation mode and applying a different level voltage to the bit line and the inverted bit line in a burn-in test operation mode. It is possible to efficiently screen defects of memory cells and between bit lines by performing a wafer burn-in test using a wafer burn-in scheme on a memory device having an open bit line cell structure.
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公开(公告)号：KR1020050033320A
公开(公告)日：2005-04-12
申请号：KR1020030069312
申请日：2003-10-06
Applicant: 삼성전자주식회사
IPC: H03K5/05
CPC classification number: G11C11/4076 , G11C7/22 , H03K5/133 , H03L7/0814
Abstract: A delay signal generation circuit is provided to reduce unnecessary power consumption and enhance energy efficiency by suppressing an operation of a fixing delay unit while a minimum delay signal having a minimum delay time is generated by only an operation of a minimum delay unit. A delay signal generation circuit includes an operation control unit for suppressing a drive current when a control signal is used for generating a minimum delay signal or providing the drive current when the control signal is not used for generating the minimum delay signal. The operation controller includes a detector(41) for detecting a control signal to generate a minimum delay signal, a bias signal breaking part(421) for suppressing the supply of driving bias signals to a fixing delay unit when the detector(41) detects the control signal to generate the minimum delay signal, a drive current breaking part(423) for suppressing the supply of the drive current to the fixing delay unit when the detector(41) detects the control signal to generate the minimum delay signal, and a delay unit(422) for operating the bias signal breaking part(421) prior to the drive current breaking part(423).
Abstract translation: 提供延迟信号发生电路以通过仅通过最小延迟单元的操作产生具有最小延迟时间的最小延迟信号，从而通过抑制固定延迟单元的操作来减少不必要的功率消耗并提高能量效率。 延迟信号发生电路包括一个操作控制单元，用于当控制信号用于产生最小延迟信号时抑制驱动电流，或者当控制信号不用于产生最小延迟信号时提供驱动电流。 操作控制器包括：检测器（41），用于检测控制信号以产生最小延迟信号;偏置信号断开部分（421），用于当检测器（41）检测到检测器（41）时，抑制向定影延迟单元提供驱动偏置信号 控制信号以产生所述最小延迟信号;驱动电流断开部分，用于当所述检测器检测到所述控制信号以产生所述最小延迟信号时，抑制向所述定影延迟单元供电的驱动电流;以及延迟 单元（422），用于在驱动电流断开部分（423）之前操作偏置信号断开部分（421）。
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公开(公告)号：KR1020160016051A
公开(公告)日：2016-02-15
申请号：KR1020140099241
申请日：2014-08-01
Applicant: 삼성전자주식회사
IPC: G11C29/42 , G11C11/401
CPC classification number: G11C29/52 , G06F11/1048 , G11C11/406 , G11C16/0466 , G11C29/42 , G11C29/44 , G11C29/50016 , G11C29/783 , G11C2211/4062
Abstract: 본발명은선택적 ECC 기능을갖는반도체메모리장치에대하여개시된다. 반도체메모리장치는메모리셀 어레이를메모리셀들의데이터리텐션특성에따라소정의블락들로분할한다. 분할된블락들중 표준에서정의된리프레쉬주기보다긴 주기의리프레쉬레이트에서발생되는불량셀들이많이분포하는블락이선택되고, 선택된블락은 ECC 기능을수행하여불량셀들을구제하고, 비선택된블락은리던던시셀들을이용하여불량셀들을구제하여, 메모리셀 어레이의메모리셀들은리프레쉬주기보다긴 주기의리프레쉬레이트로리프레쉬된다.
Abstract translation: 根据本发明，公开了具有选择性ECC功能的半导体存储器件。 半导体存储器件根据存储器单元的数据保持特性将存储单元阵列划分成预定块。 从分割块中选择其中存在以比由标准定义的刷新周期更长的周期的刷新率产生的多个缺陷单元的块。 所选择的块通过执行ECC功能来修复有缺陷的单元。 未选择的块通过使用冗余单元来修复有缺陷的单元。 因此，存储单元阵列的存储单元以比刷新周期更长的周期的刷新率刷新。
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