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公开(公告)号：KR1020170062635A
公开(公告)日：2017-06-08
申请号：KR1020150167750
申请日：2015-11-27
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: G11C5/02 , G11C5/14 , G11C7/22 , G11C11/4093
CPC classification number: G11C11/4076 , G11C5/145 , G11C11/4074 , G11C11/4096 , H02M1/14 , H02M3/07 , H03K5/131 , H03K2005/00058
Abstract: 피크전류를줄이기위해복수의메모리다이들에설치된펌프들을분산적으로제어할수 있는반도체메모리장치가개시된다. 본발명에따른반도체메모리장치는, 메모리다이에설치된적어도하나의펌프와, 펌프구동타임구간에서상기적어도하나의펌프의구동을제어하기위한펌프인에이블부를구비한다. 또한, 반도체메모리장치는상기적어도하나의펌프가상기메모리다이와다른타 메모리다이에설치된펌프와는동시에구동되지않도록하기위한펌프인에이블제어신호를생성하여상기펌프인에이블부로인가하는비중첩인에이블신호생성회로를포함한다.
Abstract translation: 公开了一种能够分散地控制安装在多个存储器管芯中的泵以减少峰值电流的半导体存储器件。 根据本发明的半导体存储器件包括安装在存储器管芯中的至少一个泵和用于在泵驱动时间间隔内控制所述至少一个泵的驱动的泵启用部分。 而且，半导体存储器件可以产生泵激活控制信号，以防止至少一个泵与安装在存储器管芯和其他存储器管芯中的泵同时被驱动，并且产生非重叠使能信号 和的电路。
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2.发明公开
公开(公告)号：KR1020170040441A
公开(公告)日：2017-04-13
申请号：KR1020150139241
申请日：2015-10-02
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: G11C5/14 , G11C5/04 , G11C11/4074
CPC classification number: G11C11/4074 , G11C5/025 , G11C5/145 , G11C11/1697 , G11C29/021 , G11C29/028 , G11C2029/0409 , H01L23/481 , H01L25/0657
Abstract: 차아지펌프의구동능력및 소모전류를타 메모리다이의동작상태정보에 따라구별적으로제어할수 있는반도체메모리장치가개시된다. 본발명에따른반도체메모리장치는, 복수의메모리다이들에각기설치된복수의차아지펌프들과, 상기복수의차아지펌프들을제어하기위해상기복수의메모리다이들에각기설치되며, 타메모리다이에대한동작상태정보를수신하여자신의메모리다이에있는상기복수의차아지펌프들을제어하기위한제어신호들을생성하는펌프매니징회로를구비한다.
Abstract translation: 公开了一种能够根据另一存储器芯片的操作状态信息分别控制电荷泵的驱动能力和消耗电流的半导体存储器件。 根据本发明的半导体存储器件包括分别安装在多个存储器管芯上的多个电荷泵和分别安装在多个存储器管芯上用于控制多个电荷泵的多个电荷泵电路， 以及泵管理电路，用于接收存储器管芯上的操作状态信息并生成用于控制其存储器管芯中的多个电荷泵的控制信号。
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公开(公告)号：KR1020080001903A
公开(公告)日：2008-01-04
申请号：KR1020060060361
申请日：2006-06-30
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: G11C7/12
Abstract: A circuit and a method for generating a control signal for a memory cell array are provided to control enable time of a bit line equalize signal regardless of disable time of a word line driving signal. A block control circuit(1100) generates a block information precharge signal with variable pulse width. A main word line driving signal generation circuit generates a main word line driving signal in response to a pulse front edge of the block information precharge signal. An equalize signal generation circuit generates a bit line equalize signal in response to the pulse back edge of the block information precharge signal.
Abstract translation: 提供用于产生用于存储单元阵列的控制信号的电路和方法，用于控制位线均衡信号的使能时间，而不管字线驱动信号的禁止时间。 块控制电路（1100）生成具有可变脉冲宽度的块信息预充电信号。 主字线驱动信号产生电路响应于块信息预充电信号的脉冲前沿产生主字线驱动信号。 均衡信号产生电路响应于块信息预充电信号的脉冲后沿产生位线均衡信号。
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公开(公告)号：KR100562504B1
公开(公告)日：2006-03-21
申请号：KR1020030060330
申请日：2003-08-29
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: G11C8/00
CPC classification number: G11C5/063
Abstract: 본 발명은 신호선의 길이 차이에 의한 신호의 위상차를 줄이기 위한 반도체 메모리 장치에 관한 것이다.
본 발명에 따른 반도체 메모리 장치는, 세로축을 중심으로 좌우 대칭 구조를 이루는 복수개의 메모리 블록들과; 상기 메모리 블록들을 구동하는 데코더들과; 상기 데코더들에 입력되는 신호들을 발생하는 신호 발생기와; 상기 신호 발생기의 출력 신호를 상기 데코더들에 전송하도록 배치된 신호선들과; 상기 세로축을 중심으로 멀리 위치한 메모리 블록들과 가까이 위치한 메모리 블록들 사이의 상기 신호선들의 길이 차이에 의한 신호의 위상차 줄이는 지연 회로를 포함하는 것을 특징으로 한다.
본 발명에 의하면, 신호선의 길이 차이에 의한 신호의 위상차 문제 및 신호선이 길어짐으로써 발생되는 고주파 특성의 저하 문제가 해결된다.-
公开(公告)号：KR1020030055996A
公开(公告)日：2003-07-04
申请号：KR1020010086147
申请日：2001-12-27
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: H01L21/60
CPC classification number: H01L24/05 , H01L2224/04042 , H01L2224/05 , H01L2224/48 , H01L2224/48091 , H01L2224/48463 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012
Abstract: PURPOSE: A semiconductor device having a member for controlling uniformly parasitic components of a bonding wire is provided to control easily the parasitic ingredients of the bonding wire without increasing a size of a chip by forming an inductor, a resistor, and a capacitor at a lower portion of a bonding pad. CONSTITUTION: A bonding pad(311) is connected to a pin(34) of a package by a bonding wire(32). An internal circuit(334) is connected to the bonding pad. An inductor(312) is formed between the bonding pad and the substrate of a lower of the bonding pad. A resistor(313) and a capacitor(314) are formed between the bonding pad and the substrate. The resistor and the capacitor are serially connected to the inductor. The inductor is formed with a metal layer.
Abstract translation: 目的：提供一种具有用于控制接合线的均匀寄生分量的部件的半导体器件，用于通过在下部形成电感器，电阻器和电容器来容易地控制接合线的寄生成分而不增加芯片的尺寸 焊盘的一部分。 构成：接合焊盘（311）通过接合线（32）连接到封装的引脚（34）。 内部电路（334）连接到接合焊盘。 在接合焊盘和焊盘的下部的基板之间形成电感器（312）。 在焊盘和基板之间形成电阻器（313）和电容器（314）。 电阻器和电容器串联连接到电感器。 电感器形成有金属层。
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Patent Agency Ranking
公开(公告)号：KR1020030031254A
公开(公告)日：2003-04-21
申请号：KR1020010063051
申请日：2001-10-12
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: H01L21/82
Abstract: PURPOSE: A semiconductor memory device having a metal layer to realign a pad is provided to embody various layouts, and to improve transmit characteristic of signals by changing resistance and capacitance of the layouts. CONSTITUTION: A semiconductor memory device is disposed on a metal layer for interconnection. The metal layer for interconnection includes the first metal line, the second metal line. Capacitance between the first and second metal line is increased by realigning the first and second metal line.
Abstract translation: 目的：提供一种具有重新排列焊盘的金属层的半导体存储器件，以体现各种布局，并通过改变布局的电阻和电容来改善信号的传输特性。 构成：半导体存储器件设置在用于互连的金属层上。 用于互连的金属层包括第一金属线，第二金属线。 通过重新对准第一和第二金属线来增加第一和第二金属线之间的电容。
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公开(公告)号：KR1020010054445A
公开(公告)日：2001-07-02
申请号：KR1019990055258
申请日：1999-12-06
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: G11C7/06
Abstract: PURPOSE: A current sense amplifier of a semiconductor memory device is provided to reduce of a current consumption by limiting the amount of a current supplied to a sensing line with a simple circuit configuration. CONSTITUTION: A cell current control circuit(30) comprises a PMOS transistor(P20) and NMOS transistors(N20,N21), and a current mirror(32) comprises PMOS transistors(P21,P22,P23) and an NMOS transistor(N25). And a current mirror(34) comprises a PMOS transistor(P23) and NMOS transistors(N23,N24). A reference current control circuit(36) comprises a PMOS transistor(P25) and NMOS transistors(N26,N27). The amplifier also comprises an NMOS transistor(N22) and inverters(I3,I4). A voltage(VPP) applied to a dummy floating gate memory cell is a word line voltage level higher than a power supply voltage(VCC). The cell current control circuit changes a conductance of the PMOS transistor(P23) and the NMOS transistor(N22). The PMOS transistor induces a voltage between the current mirror(34) and a sensing line(24), and changes the conductance properly to the current intensity of the current mirror(34).
Abstract translation: 目的：提供半导体存储器件的电流检测放大器，通过以简单的电路配置限制提供给感测线的电流量来减少电流消耗。 构成：电池电流控制电路（30）包括PMOS晶体管（P20）和NMOS晶体管（N20，N21），电流镜（32）包括PMOS晶体管（P21，P22，P23）和NMOS晶体管（N25） 。 并且电流镜（34）包括PMOS晶体管（P23）和NMOS晶体管（N23，N24）。 参考电流控制电路（36）包括PMOS晶体管（P25）和NMOS晶体管（N26，N27）。 放大器还包括NMOS晶体管（N22）和反相器（I3，I4）。 施加到虚拟浮动栅极存储单元的电压（VPP）是比电源电压（VCC）高的字线电压电平。 电池电流控制电路改变PMOS晶体管（P23）和NMOS晶体管（N22）的电导。 PMOS晶体管在电流镜（34）和感测线（24）之间感应电压，并将电导正确地改变为电流镜（34）的电流强度。
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公开(公告)号：KR1020100043490A
公开(公告)日：2010-04-29
申请号：KR1020080102542
申请日：2008-10-20
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: G11C11/4074 , G11C11/407 , G11C11/4093 , G11C11/4091
CPC classification number: G11C11/4094 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4091
Abstract: PURPOSE: A precharge control circuit and a control method thereof are provided to normally execute an active operation and a precharge operation by stopping the operation of a bit line sensing amplifier using a pulse back edge of a sub word line precharge pulse signal. CONSTITUTION: A sub word line drive control circuit(210) precharges a voltage of bit line pair and answers to a signal directing a precharge operation. The sub word line drive control circuit generates a sub word line precharge pulse signal resetting the sub word line driving signal driving the sub word line. A delay circuit(220) delays the sub word line precharge pulse signal. The delay circuit generates a block selection precharge pulse signal resetting the block selection signal. A precharge/equalizing signal generating circuit responds to the sub word line precharge pulse signal, and a pulse back edge of the block selection precharge pulse signal. The precharge/equalizing signal generating circuit(500) generates the precharge/equalization signal and precharges a voltage of a bit line pair.
Abstract translation: 目的：提供一种预充电控制电路及其控制方法，以通过使用子字线预充电脉冲信号的脉冲后沿停止位线检测放大器的操作来正常执行有效操作和预充电操作。 构成：子字线驱动控制电路（210）对位线对的电压进行预充电，并对指示预充电操作的信号进行应答。 子字线驱动控制电路产生副字线预充电脉冲信号，复位驱动子字线的子字线驱动信号。 延迟电路（220）延迟子字线预充电脉冲信号。 延迟电路产生块选择预充电脉冲信号，复位块选择信号。 预充电/均衡信号发生电路响应子字线预充电脉冲信号和块选择预充电脉冲信号的脉冲后沿。 预充电均衡信号产生电路（500）产生预充电/均衡信号并对位线对的电压进行预充电。
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公开(公告)号：KR1020060116266A
公开(公告)日：2006-11-15
申请号：KR1020050038268
申请日：2005-05-09
Applicant: 삼성전자주식회사
Inventor： 박민상
IPC: G11C7/10
Abstract: An input/output multiplexer of a memory device is provided to compensate the difference of resistance and parasitic capacitance according to the length difference of a global input/output line by using a parallel interconnection of a MOS transistor and a global input/output line length discrimination signal. A global input/output line length discrimination signal generation part(130) generates a global input/output line length discrimination signal capable of discriminating the length of a global input/output line. A first MOS transistor(101) is installed between the global input/output line and a data input/output line, and is turned on/off according to a line selection signal applied from the outside. A second MOS transistor(103) is connected in parallel with the first MOS transistor, and is turned on/off according to the global input/output line length discrimination signal.
Abstract translation: 提供存储器件的输入/输出多路复用器，以通过使用MOS晶体管的并联互连和全局输入/输出线路长度鉴别来根据全局输入/输出线的长度差来补偿电阻和寄生电容的差异 信号。 全局输入/输出线路长度鉴别信号产生部分（130）产生能够区分全局输入/输出线路的长度的全局输入/输出线路长度鉴别信号。 第一MOS晶体管（101）安装在全局输入/输出线和数据输入/输出线之间，并且根据从外部施加的线选信号而导通/截止。 第二MOS晶体管（103）与第一MOS晶体管并联连接，并根据全局输入/输出线长度鉴别信号导通/截止。
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公开(公告)号：KR100572320B1
公开(公告)日：2006-04-19
申请号：KR1020030068878
申请日：2003-10-02
Applicant: 삼성전자주식회사
IPC: G11C11/40
Abstract: 본 발명은 반도체메모리장치에 관한 것이다.
본 발명은 리드용 데이터경로와 라이트용 데이터경로 분리함으로써 다수 개의 뱅크를 갖는 반도체메모리장치에서 어느 하나의 뱅크에 데이터를 라이트하면서 동시에 다른 어느 뱅크에 저장되어 있는 데이터를 리드할 수 있는 반도체메모리장치를 개시한다.
어드레스, 뱅크어드레스, 프리디코더, 뱅크, 라이트드라이버Abstract translation: 本发明涉及一种半导体存储器件。
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