公开(公告)号：KR1020140066535A

公开(公告)日：2014-06-02

申请号：KR1020120133904

申请日：2012-11-23

Applicant: 삼성전자주식회사

Inventor： 박선아 ,  최윤호

IPC: G06F9/44 ,  G06F1/32 ,  G06F13/14

CPC classification number: G06F9/4411 ,  G06F8/654 ,  G06F9/4418 ,  G06F12/0246 ,  Y02D10/42 ,  Y02D10/44 ,  G06F1/3225 ,  G06F8/70 ,  G06F13/14

Abstract: An electronic apparatus is disclosed. The electronic apparatus of the present invention comprises: a function unit which stores firmware; a communication interface unit which receives a new firmware to be updated; a control unit which converts the operation mode of the electronic apparatus into a power saving mode; and an updating unit which updates the firmware of the function unit using a new firmware which is received while the operation mode of the electronic apparatus returns from the power saving mode to a normal mode.

Abstract translation: 公开了一种电子设备。 本发明的电子设备包括：存储固件的功能单元; 接收要更新的新固件的通信接口单元; 控制单元，其将电子设备的操作模式转换为省电模式; 以及更新单元，其使用在电子设备的操作模式从节电模式返回到正常模式时接收到的新固件来更新功能单元的固件。

公开(公告)号：KR102123283B1

公开(公告)日：2020-06-16

申请号：KR1020160104827

申请日：2016-08-18

Applicant: 삼성전자주식회사

Inventor： 양동일 ,  임원섭 ,  김대영 ,  박선아 ,  오승현

IPC: H01Q1/24 ,  H04M1/725 ,  H01Q1/52

公开(公告)号：KR1020020017322A

公开(公告)日：2002-03-07

申请号：KR1020000050548

申请日：2000-08-29

Applicant: 삼성전자주식회사

Inventor： 문경하 ,  유수경 ,  황제환 ,  김영익 ,  박선아 ,  김서영

IPC: G02F1/133

CPC classification number: G02F1/1345 ,  G02F1/136204 ,  G09G3/3648 ,  G09G2330/04

Abstract: PURPOSE: A structure of a control signal part and a liquid crystal display having the same are provided to form a high voltage redundancy line for generating a high voltage and a same potential at a peripheral part of a high voltage signal line, thereby preventing the damage of the high voltage signal line due to the electrolysis. CONSTITUTION: A structure of a control signal part includes a first signal line(201) applied with a first signal voltage, a second signal line applied with a second signal voltage(202) smaller than the first signal voltage, a first redundancy line(210) positioned between the first signal line and the second signal line and applied with a voltage equal to the first signal voltage, and a second redundancy line(220) at the other side of the first signal line and applied with a voltage equal to the first signal voltage.

Abstract translation: 目的：提供控制信号部分的结构和具有该结构的液晶显示器，以形成用于在高电压信号线的周边部分产生高电压和相同电位的高电压冗余线，从而防止损坏 的高压信号线由于电解。 构成：控制信号部分的结构包括施加有第一信号电压的第一信号线（201），施加有小于第一信号电压的第二信号电压（202）的第二信号线，第一冗余线（210 ），位于第一信号线和第二信号线之间并施加与第一信号电压相等的电压，以及在第一信号线的另一侧施加第二冗余线（220），并施加与第一信号线相同的电压 信号电压。

公开(公告)号：KR1020010054137A

公开(公告)日：2001-07-02

申请号：KR1019990054790

申请日：1999-12-03

Applicant: 삼성전자주식회사

Inventor： 박선아

IPC: G06F13/24

Abstract: PURPOSE: A method for controlling a bus is provided to enhance system efficiency by preventing a data transmitting speed from being decreased on a bus line. CONSTITUTION: A serial clock control unit(2) and a data control unit(4) transmit/receive a SCL and a SD being exchanged thereto on a bus. A serial clock free scalar(5) decides a SCL frequency. The elements included in the internal register unit(10) are described as follows. A free scalar register(11) stores a SCL frequency. An interrupt register(12) indicates a receiving completion, a transmitting completion, a FIFO empty, a FIFO full, and a response. A control register(13) controls a transmitting mode, a receiving mode, a response enable, a data transmitting start, a stop, a busy, a consecutiveness, and a reset. A FIFO control register(16) controls a FIFO empty, a full, a flush etc. A FIFO transmitting/receiving register(17) stores an address to be transmitted. In addition, the internal register unit(10) includes a counter register(14), a buffer register(15) and a FIFO register(18). A shift buffer register(6) shifts data(3:0) being transmitted/received through the bus and transmits or receives the data to a SCL. A FIFO register(18) consists of 32-bit.

Abstract translation: 目的：提供一种控制总线的方法，以通过防止总线上的数据传输速度降低来提高系统效率。 构成：串行时钟控制单元（2）和数据控制单元（4）在总线上发送/接收与其交换的SCL和SD。 串行时钟自由标量（5）决定SCL频率。 包括在内部寄存器单元（10）中的元件被描述如下。 自由标量寄存器（11）存储SCL频率。 中断寄存器（12）指示接收完成，发送完成，FIFO空，FIFO满和响应。 控制寄存器（13）控制发送模式，接收模式，响应使能，数据发送开始，停止，忙，连续性和复位。 FIFO控制寄存器（16）控制FIFO为空，满，闪存等。FIFO发送/接收寄存器（17）存储要发送的地址。 此外，内部寄存器单元（10）包括计数器寄存器（14），缓冲寄存器（15）和FIFO寄存器（18）。 移位缓冲寄存器（6）通过总线移位正在发送/接收的数据（3：0），并将数据发送或接收到SCL。 FIFO寄存器（18）由32位组成。