公开(公告)号：KR1020080015184A

公开(公告)日：2008-02-19

申请号：KR1020060076570

申请日：2006-08-14

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G06F7/58 ,  G06F7/00

CPC classification number: G06F7/588 ,  H03B29/00 ,  H03K3/84 ,  H03K5/135

Abstract: A random number generator including a random signal generator is provided to make other special offset elimination unnecessary and to be operable with a low voltage. A random signal generator comprises a noise source(110), a self-biased inverter(130) and an amplifying circuit(150). The noise source(110) generates irregular noise signals. The self-biased inverter gets self-biased by connecting an input terminal to an output terminal, and outputs a sensed noise signal by sensing the noise signal transmitted to the input terminal. The amplifying circuit amplifies the sensed noise signal and outputs a random signal whose logical high level and low level have irregular continuing time. The self-biased inverter includes a resistor connected between the input terminal and the output terminal.

Abstract translation: 提供包括随机信号发生器的随机数发生器，以便不需要其他特殊的偏移消除并且可以以低电压工作。 随机信号发生器包括噪声源（110），自偏置逆变器（130）和放大电路（150）。 噪声源（110）产生不规则的噪声信号。 通过将输入端子连接到输出端子，自偏置逆变器得到自偏置，并且通过感测传输到输入端子的噪声信号来输出感测到的噪声信号。 放大电路对感测到的噪声信号进行放大并输出其逻辑高电平和低电平具有不规则持续时间的随机信号。 自偏置逆变器包括连接在输入端子和输出端子之间的电阻器。

公开(公告)号：KR1020070087987A

公开(公告)日：2007-08-29

申请号：KR1020060018026

申请日：2006-02-24

Applicant: 삼성전자주식회사

Inventor： 정무경 ,  신순균

IPC: H03K19/00 ,  H03K19/094

CPC classification number: H03F1/223 ,  H03F3/345

Abstract: A low voltage regulated cascade circuit and a CMOS analog circuit using the same are provided to maintain a high output resistance and a wide output voltage swing width at an operation voltage under one volt by maintaining a higher threshold voltage than the threshold voltage of NMOS transistors. A low voltage regulated cascade circuit includes a first MOS transistor(NM2), a second MOS transistor(NM1), a third MOS transistor(PM1), and a first current source(CS2). The first MOS transistor(NM2) of a first conductive type is connected between an output terminal and a first node. The second MOS transistor(NM1) of a first conductive type applies a bias voltage to a gate and is connected between the first node and a second power terminal. A third MOS transistor(PM1) of a second conductive type different from the first conductive type is connected between a first power terminal and a gate of the first MOS transistor(NM2). The first current source(CS2) is connected between a second power voltage and the gate of the first MOS transistor(NM2).

Abstract translation: 通过保持比NMOS晶体管的阈值电压更高的阈值电压，提供低压调节级联电路和使用其的CMOS模拟电路，以在一伏特的工作电压下保持高的输出电阻和宽的输出电压摆幅宽度。 低压调节级联电路包括第一MOS晶体管（NM2），第二MOS晶体管（NM1），第三MOS晶体管（PM1）和第一电流源（CS2）。 第一导电类型的第一MOS晶体管（NM2）连接在输出端和第一节点之间。 第一导电类型的第二MOS晶体管（NM1）向栅极施加偏置电压并连接在第一节点和第二电源端子之间。 与第一导电类型不同的第二导电类型的第三MOS晶体管（PM1）连接在第一MOS晶体管（NM2）的第一电源端子和栅极之间。 第一电流源（CS2）连接在第二电源电压和第一MOS晶体管（NM2）的栅极之间。

公开(公告)号：KR100519788B1

公开(公告)日：2005-10-10

申请号：KR1020020079348

申请日：2002-12-12

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C7/10

CPC classification number: H03K19/00315

Abstract: 본 발명은 입력 버퍼를 공개한다. 이 회로는 전원전압과 패드사이에 연결되고 제어전압이 인가되는 게이트와 플로팅 웰 전압이 인가되는 기판을 가진 풀업 트랜지스터, 전원전압이 인가되는 게이트와 접지전압에 연결된 기판을 가지고 패드로 인가되는 신호를 전송하는 전송 트랜지스터, 전송 트랜지스터로 인가되는 신호를 버퍼하여 입력 신호를 발생하는 버퍼, 및 패드로 고전압이 인가되면 패드로 인가되는 전압을 제어전압 및 플로팅 웰 전압으로 발생하고, 패드로 고전압미만의 전압이 인가되면 제어전압으로 접지전압을, 플로팅 웰 전압으로 전원전압을 발생하는 제어회로로 구성되어 있다. 따라서, 패드가 플로팅 상태로 되는 경우에 패드를 전원전압 레벨로 풀업함으로써 외부의 장치의 패드에 연결된 입력 버퍼를 통한 누설 전류를 방지할 수 있으며, 패드로 고전압이 인가되는 경우에 풀업 트랜지스터가 오프됨으로써 풀업 트랜지스터가 고전압으로부터 보호될 수 있다.

公开(公告)号：KR1020040026726A

公开(公告)日：2004-04-01

申请号：KR1020020058250

申请日：2002-09-25

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C7/10

CPC classification number: H03K19/00315

Abstract: PURPOSE: An input/output circuit of a semiconductor device is provided to perform a tolerant function during power-on/off. CONSTITUTION: A control signal generator unit(36) generates the first control signal of a power supply voltage level, the second control signal of a ground voltage level and the third control signal of a high voltage level during power-on when a high voltage is applied through a pad(42-1), and generates the first and the second control signals of the power supply voltage level and the third control signal of the high voltage level during power-off. An output buffer(38-1,...,38-n) comprises the first and the second pull-up transistor, the first and the second pull-down transistor, a pre-driver pulling up/down the pad when an output enable signal is activated and turning off the pull-up transistors and the pull-down transistors when the output enable signal is disabled, and the first tolerant and current flow prevention unit controlling a voltage difference between a gate and a source/drain of the pull-up transistors and the pull-down transistors and preventing current flow to the power supply voltage from the pad. And an input buffer(40-1,...,40-n) comprises the third and the fourth and the fifth pull-up transistors, the third pull-down transistor, and the second tolerant and current flow prevention unit controlling the voltage difference between a gate and a source/drain of the third and the fourth and the fifth pull-up transistor and the third pull-down transistor and preventing the current flow to the power supply voltage from the pad.

Abstract translation: 目的：提供半导体器件的输入/输出电路以在上电/断电期间执行容限功能。 构成：当高压为高电平时，控制信号发生器单元（36）产生电源电压电平的第一控制信号，接地电压电平的第二控制信号和高电压电平的第三控制信号， 通过焊盘（42-1）施加，并且在断电期间产生电源电压电平和高电压电平的第三控制信号的第一和第二控制信号。 输出缓冲器（38-1，...，38-n）包括第一和第二上拉晶体管，第一和第二下拉晶体管，当驱动器的输出 当输出使能信号被禁止时，使能信号被激活并且关断上拉晶体管和下拉晶体管，并且第一容限和电流流动防止单元控制栅极和引脚的源极/漏极之间的电压差 - 晶体管和下拉晶体管，并防止电流从焊盘流向电源电压。 并且输入缓冲器（40-1，...，40-n）包括第三和第四和第五上拉晶体管，第三下拉晶体管和第二容限和电流防止单元，控制电压 第三和第四和第五上拉晶体管和第三下拉晶体管的栅极和源极/漏极之间的差异，并且防止电流从焊盘流向电源电压。

公开(公告)号：KR1020020066841A

公开(公告)日：2002-08-21

申请号：KR1020010007274

申请日：2001-02-14

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C11/40

CPC classification number: H03K19/00384

Abstract: PURPOSE: An output buffer circuit for minimizing a variation of a slew rate due to a variation of PVT and a variation of load capacitance of an output terminal is provided to reduce the variation of slew rate and protect gate oxide layers of transistors from voltage higher than supply voltage. CONSTITUTION: A bias voltage generator(21) generates the first bias voltage(Nbias) and the second bias voltage(Pbias) by using reference voltage. The first slew rate control portion(23) controls a pull-up slew rate of an output driver(22) in response to output data(D) and the first bias voltage(Nbias). The second slew rate control portion(24) controls a pull-down slew rate in response to output data(D) and the second bias voltage(Pbias). The output driver(22) is formed with a pull-up driver(22a) and a pull-down driver(22b). The output driver(22) drives an output terminal(28) in response to an output signal(SC1) of the first slew rate control portion(23) and an output signal(SC2) of the second slew rate control portion(24). A slew rate compensation portion(25) compensates a variation of slew rate according to a variation of load capacitance of the output terminal(28). A high voltage protection portion(26) protects gate oxide layers of transistors from voltage higher than supply voltage.

Abstract translation: 目的：提供一种用于最小化PVT变化和输出端子负载电容变化的转换速率变化的输出缓冲电路，以减小压摆率的变化，并保护晶体管的栅氧化层免受高于 电源电压。 构成：偏置电压发生器（21）通过使用参考电压产生第一偏置电压（Nbias）和第二偏置电压（Pbias）。 第一压摆率控制部分（23）响应于输出数据（D）和第一偏置电压（Nbias）来控制输出驱动器（22）的上拉转换速率。 第二压摆率控制部分（24）响应于输出数据（D）和第二偏置电压（Pbias）来控制下拉压摆率。 输出驱动器（22）形成有上拉驱动器（22a）和下拉驱动器（22b）。 输出驱动器（22）响应于第一转换速率控制部分（23）的输出信号（SC1）和第二转换速率控制部分（24）的输出信号（SC2）驱动输出端子（28）。 压摆率补偿部分（25）根据输出端子（28）的负载电容的变化来补偿压摆率的变化。 高电压保护部分（26）保护晶体管的栅极氧化物层的电压高于电源电压。

公开(公告)号：KR100706576B1

公开(公告)日：2007-04-13

申请号：KR1020050070345

申请日：2005-08-01

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K17/166

Abstract: 슬루율 제어가 가능한 반도체 집적회로의 출력 구동회로가 개시되어 있다. 반도체 집적회로의 출력 구동회로는 프리 드라이버, 및 메인 드라이버를 구비한다. 프리 드라이버는 제 1 입력신호를 버퍼링하여 제 1 게이트 제어신호를 발생시켜 제 1 노드에 제공하고, 제 2 입력신호를 버퍼링하여 제 2 게이트 제어신호를 발생시켜 제 2 노드에 제공한다. 메인 드라이버는 제 1 게이트 제어신호 및 제 2 게이트 제어신호에 응답하여 출력신호를 발생시켜 출력노드에 제공한다. 출력신호가 상승 천이하는 동안 출력노드와 상기 제 1 노드 사이에 제 1 용량성 전류 경로가 형성되고, 출력신호가 하강 천이하는 동안 출력노드와 제 2 노드 사이에 제 2 용량성 전류 경로가 형성된다. 따라서, 출력 구동회로는 공정, 전압, 온도 등의 동작환경에 무관하게 일정한 슬루율을 가지는 출력신호를 발생시킬 수 있다.

公开(公告)号：KR100438773B1

公开(公告)日：2004-07-05

申请号：KR1020010053271

申请日：2001-08-31

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C11/40

CPC classification number: H03L7/0805 ,  H03K5/133 ,  H03K19/00384 ,  H03K2005/00039 ,  H03L7/0995

Abstract: An output buffer circuit for reducing a variation of the slew rate due to a variation of process, voltage and temperature (PVT) and the load capacitance of an output terminal, and semiconductor device including the same, include a first slew rate control circuit for pulling down the voltage of a pull-up signal in multiple stages in response to a first control signal, and a second slew rate control circuit for pulling up the voltage of a pull-down signal in multiple stages in response to a second control signal. A pull-up driver is provided for pulling up an output terminal in response to the pull-up signal, and a pull-down driver is provided for pulling down the output terminal in response to the pull-down signal. The first and second slew rate control circuits are controlled by bias voltages that are provided by a phase locked loop circuit and compensate for changes in PVT.

Abstract translation: 用于减小由于工艺，电压和温度（PVT）和输出端子的负载电容的变化而引起的转换速率的变化的输出缓冲电路以及包括该输出缓冲电路的半导体器件包括第一转换速率控制电路和第二转换速率控制电路， 响应于第一控制信号而在多级中下拉上拉信号的电压;以及第二转换速率控制电路，用于响应于第二控制信号以多级上拉下拉信号的电压。 提供上拉驱动器用于响应于上拉信号拉高输出端子，并且提供下拉驱动器用于响应于下拉信号拉低输出端子。 第一和第二转换速率控制电路由锁相环电路提供的偏置电压控制并补偿PVT的变化。

公开(公告)号：KR100439041B1

公开(公告)日：2004-07-03

申请号：KR1020020058250

申请日：2002-09-25

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C7/10

CPC classification number: H03K19/00315

Abstract: An input and output circuit of a semiconductor device is disclosed having an output buffer including first and second pull-up transistors connected in series between the power supply voltage and the pad, first and second pull-down transistors connected in series between the pad and the ground voltage, a pre-driver for pulling up or down a voltage of the pad when an output enable signal is enabled and for switching off the first and second pull-up transistors and the first and second pull-down transistors when the output enable signal is disabled, and a first circuit for adjusting voltage differences between respective gates and respective sources/drains of the first and second pull-up transistors and the first and second pull-down transistors to be below a predetermined voltage level in response to the first, second and third control signals under power on or power off conditions; and an input buffer including a transmission gate for transmitting an input signal applied to the pad to a first node in response to the first control signal, third, fourth and fifth pull-up transistors connected in series between the power supply voltage and a second node and having corresponding gates connected to a third node, the pad and the first node, respectively, a third pull-down transistor connected between the second node and the ground voltage and having a gate connected to the first node, a second circuit for adjusting voltage differences between respective gates and respective sources/drains of the third, fourth and fifth pull-up transistors and the third pull-down transistor to be below a predetermined voltage in response to the first and third control signals if the high voltage is applied to the pad under either power on or power off conditions.

Abstract translation: 公开了一种半导体器件的输入和输出电路，其具有包括串联连接在电源电压和焊盘之间的第一和第二上拉晶体管的输出缓冲器，串联连接在焊盘和焊盘之间的第一和第二下拉晶体管 地电压;预驱动器，用于当输出使能信号被使能时上拉或下拉所述焊盘的电压，并且用于当所述输出使能信号被关断时关断所述第一和第二上拉晶体管以及所述第一和第二下拉晶体管 以及第一电路，用于响应于所述第一和第二上拉晶体管以及所述第一下拉晶体管和所述第二下拉晶体管的相应栅极和相应源极/漏极之间的电压差而低于预定电压电平， 第二和第三控制信号在通电或断电条件下; 以及包括传输门的输入缓冲器，用于响应串联连接在电源电压和第二节点之间的第一控制信号，第三，第四和第五上拉晶体管，将施加到焊盘的输入信号传输到第一节点 并且具有分别连接到第三节点，焊盘和第一节点的相应的栅极，连接在第二节点和地电压之间并具有连接到第一节点的栅极的第三下拉晶体管，用于调整电压的第二电路 响应于第一和第三控制信号，如果高电压被施加到第三，第四和第五上拉晶体管和第三下拉晶体管的相应栅极和相应源极/漏极之间的差值低于预定电压 在打开或关闭电源的条件下打开。

公开(公告)号：KR101163457B1

公开(公告)日：2012-07-18

申请号：KR1020060018026

申请日：2006-02-24

Applicant: 삼성전자주식회사

Inventor： 정무경 ,  신순균

IPC: H03K19/00 ,  H03K19/094

CPC classification number: H03F1/223 ,  H03F3/345

Abstract: 저전압 레귤레이티드 캐스코드 회로를 개시한다. 본 발명의 회로는 본 발명의 목적을 달성하기 위하여 제1전원단자와 출력단자 사이에 연결된 제1전류원과, 출력단자와 제1노드 사이에 연결된 제1모스 트랜지스터와, 게이트에 바이어스 전압이 인가되고 제1노드와 제2전원단자 사이에 연결된 제2모스 트랜지스터와, 제1전원단자와 상기 제1모스 트랜지스터의 게이트 사이에 연결된 제3모스 트랜지스터와, 제1모스 트랜지스터의 게이트와 제2전원전압 사이에 연결된 제2전류원을 포함한다. 따라서, 1V 이하의 저전압에서도 높은 출력저항과 넓은 전압 스윙폭을 유지하면서도 안정된 동작특성을 유지할 수 있다.

公开(公告)号：KR1020030018742A

公开(公告)日：2003-03-06

申请号：KR1020010053271

申请日：2001-08-31

Applicant: 삼성전자주식회사

Inventor： 신순균

IPC: G11C11/40

CPC classification number: H03L7/0805 ,  H03K5/133 ,  H03K19/00384 ,  H03K2005/00039 ,  H03L7/0995

Abstract: PURPOSE: An output buffer circuit for reducing slew rate variation owing to variation of load capacitance of output terminal and PVT variation and semiconductor device having the same are provided to reduce slew rate variation owing to PVT variation and variation of load capacitance of an output terminal. CONSTITUTION: A pull-up driver(P6) pulls up an output terminal(41) in response to a pull-up signal, and a pull-down driver(N6) pulls down the output terminal in response to the pull-down signal. The first slew rate control circuit(271) makes a voltage level of the pull-up signal be lowered stepwise in response to the first control signal(PC). The second slew rate control circuit(272) makes a voltage level of the pull-down signal(NG) be increased stepwise in response to the second control signal(NC).

Abstract translation: 目的：提供一种用于减少由于输出端子和PVT变化的负载电容变化而导致的转换速率变化的输出缓冲电路，以减少由于PVT变化和输出端子的负载电容变化引起的压摆率变化。 构成：上拉驱动器（P6）响应于上拉信号上拉输出端子（41），并且下拉驱动器（N6）响应于下拉信号拉下输出端子。 第一压摆率控制电路（271）响应于第一控制信号（PC）使上拉信号的电压电平逐步降低。 第二转换速率控制电路272使得下拉信号（NG）的电压电平响应于第二控制信号（NC）逐步增加。