公开(公告)号：KR1020020003608A

公开(公告)日：2002-01-15

申请号：KR1020000034259

申请日：2000-06-21

Applicant: 삼성전자주식회사

Inventor： 이동훈 ,  한승훈 ,  신헌

IPC: H01L21/8242

Abstract: PURPOSE: A method of fabricating a merged DRAM with logic for improving a refresh characteristic is provided to improve a refresh characteristic of a DRAM without degrading a transistor characteristic of a logic circuit. CONSTITUTION: An interlayer dielectric(110) is formed on a semiconductor substrate(100). A photo-resist layer is formed on the interlayer dielectric(110). A photo-resist pattern having an opening is formed on the interlayer dielectric(110) by using a photo-lithography method. A contact hole(115) is formed by etching an exposed portion of the interlayer dielectric(110). A drain region or a source region(105) is exposed by the contact hole(115). The photo-resist pattern is removed by performing an ashing process and a strip process. A nitride layer(130') is formed on a surface of the whole structure. A nitride spacer(130') is formed on a sidewall of the contact hole(115) by removing a part of the nitride layer(130'). A refresh characteristic of a DRAM is improved by performing the ashing process.

Abstract translation: 目的：提供一种制造具有用于提高刷新特性的逻辑的合并DRAM的方法，以改善DRAM的刷新特性，而不降低逻辑电路的晶体管特性。 构成：在半导体衬底（100）上形成层间电介质（110）。 在层间电介质（110）上形成光致抗蚀剂层。 通过使用光刻法在层间电介质（110）上形成具有开口的光刻胶图案。 通过蚀刻层间电介质（110）的暴露部分形成接触孔（115）。 漏极区域（105）由接触孔（115）露出。 通过进行灰化处理和剥离处理来去除光刻胶图案。 在整个结构的表面上形成氮化物层（130'）。 通过去除氮化物层（130'）的一部分，在接触孔（115）的侧壁上形成氮化物间隔物（130'）。 通过执行灰化处理来提高DRAM的刷新特性。

公开(公告)号：KR1020020003607A

公开(公告)日：2002-01-15

申请号：KR1020000034258

申请日：2000-06-21

Applicant: 삼성전자주식회사

Inventor： 신헌 ,  한승훈 ,  이동훈

IPC: H01L27/10

Abstract: PURPOSE: An insulating layer structure of a semiconductor device of merged logic with DRAM is provided to prevent diffusion of positive ions to the surface of a semiconductor substrate by using a barrier layer. CONSTITUTION: An isolation layer(150) is formed on a semiconductor substrate(100). A gate insulating layer(210), a gate(220), and a drain/source region(230) are formed on an active region of the semiconductor substrate(100). A barrier layer(310) is formed on the semiconductor substrate(100) in order to cover the gate(220). The barrier layer(310) is formed with a PE-SiON layer. The first interlayer dielectric(330) and the second interlayer dielectric(350) are formed on the barrier layer(310). The first and the second interlayer dielectrics(330,350) are planarized by performing a CMP(Chemical Mechanical Polishing) process.

Abstract translation: 目的：提供具有DRAM的合并逻辑的半导体器件的绝缘层结构，以防止通过使用阻挡层将正离子扩散到半导体衬底的表面。 构成：在半导体衬底（100）上形成隔离层（150）。 在半导体衬底（100）的有源区上形成栅极绝缘层（210），栅极（220）和漏极/源极区（230）。 为了覆盖栅极（220），在半导体衬底（100）上形成阻挡层（310）。 阻挡层（310）由PE-SiON层形成。 第一层间电介质（330）和第二层间电介质（350）形成在阻挡层（310）上。 通过执行CMP（化学机械抛光）工艺来平坦化第一和第二层间电介质（330,350）。

公开(公告)号：KR1020030048870A

公开(公告)日：2003-06-25

申请号：KR1020010078915

申请日：2001-12-13

Applicant: 삼성전자주식회사

Inventor： 신헌

IPC: H01L21/82

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of simplifying manufacturing processes and improving the reliability of fuse formation and operation by simultaneously carrying out an etching process at a fuse and pad region using photosensitive polyimide as a mask. CONSTITUTION: After depositing a lower wiring layer on a substrate(110), a lower wiring and a fuse(125) are formed by patterning the lower wiring layer. After forming an interlayer dielectric(120) on the resultant structure, an upper wiring and a pad are formed by depositing and patterning an upper wiring layer on the interlayer dielectric. A protecting layer(160,165) and a photosensitive protecting polyimide layer(191) are sequentially formed on the resultant structure. After forming a protecting polyimide pattern by selectively patterning the protecting polyimide layer, the protecting layer is etched by using the protecting polyimide pattern as a mask for exposing the pad.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，其能够通过使用光敏聚酰亚胺作为掩模在熔丝和焊盘区域同时进行蚀刻工艺来简化制造工艺并提高熔丝形成和操作的可靠性。 构成：在基板（110）上沉积下布线层之后，通过图案化下布线层形成下布线和熔丝（125）。 在所得结构上形成层间电介质（120）之后，通过沉积和图案化层间电介质上的上布线层来形成上布线和焊盘。 在所得结构上依次形成保护层（160,165）和光敏保护聚酰亚胺层（191）。 在通过选择性地图案化保护性聚酰亚胺层形成保护性聚酰亚胺图案之后，通过使用保护性聚酰亚胺图案作为掩模来掩模来蚀刻保护层。