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公开(公告)号：KR1020140064546A
公开(公告)日：2014-05-28
申请号：KR1020120131980
申请日：2012-11-20
Applicant: 삼성전자주식회사
CPC classification number: G06F12/06 , G06F2212/205 , G11C11/005 , G11C2029/4402
Abstract: A computer system according to an embodiment of the present invention includes a semiconductor memory device which includes a first memory block and a second memory block different from the first memory block; a memory controller which accesses the first and second memory blocks by using an address signal; and a central processing unit which allocates a memory space for system operation in the first memory block and another memory space for data storage in the second memory block through the memory controller. Accordingly, the computer system can easily access a semiconductor memory device.
Abstract translation: 根据本发明的实施例的计算机系统包括半导体存储器件，其包括第一存储器块和与第一存储器块不同的第二存储器块; 存储器控制器，其通过使用地址信号来访问第一和第二存储器块; 以及中央处理单元，其通过存储器控制器在第一存储器块中分配用于系统操作的存储器空间和用于数据存储的另一存储器空间。 因此，计算机系统可以容易地访问半导体存储器件。
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2.发明公开오토 리프레쉬 커맨드를 사용하지 않고 리프레쉬를 수행할 수 있는 반도체 메모리 장치 및 이를 포함하는 메모리 시스템 审中-实审不具有自动刷新命令和包括其中的存储系统的执行刷新操作的半导体存储器件
公开(公告)号：KR1020140036620A
公开(公告)日：2014-03-26
申请号：KR1020120102936
申请日：2012-09-17
Applicant: 삼성전자주식회사
IPC: G11C11/401 , G11C11/4063 , G11C11/4091 , G11C11/4096
CPC classification number: G11C11/34 , G11C8/18 , G11C11/40615 , G11C11/40618
Abstract: A semiconductor memory device capable of performing a refresh operation without an auto refresh command and a memory system including the same are disclosed. The semiconductor memory device comprises an inner address generation circuit, an inner command generation circuit, and a memory cell array. A first memory bank group and the other memory bank(s) can perform the refresh operation when a read or a write command is inputted or when a portion of the memory bank(s) of the first memory bank group performs a read or a write operation. Therefore, for the semiconductor memory device, addressing is simple, all data bandwidth can be used, and latency does not change.
Abstract translation: 公开了一种能够执行没有自动刷新命令的刷新操作的半导体存储器件和包括该刷新命令的存储器系统。 半导体存储器件包括内部地址生成电路，内部命令生成电路和存储单元阵列。 当输入读取或写入命令时，或者当第一存储器组的存储器组的一部分执行读取或写入时，第一存储器组和其它存储器组可以执行刷新操作 操作。 因此，对于半导体存储器件，寻址简单，可以使用所有数据带宽，并且延迟不变。
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3.发明公开
公开(公告)号：KR1020140012317A
公开(公告)日：2014-02-03
申请号：KR1020120078837
申请日：2012-07-19
Applicant: 삼성전자주식회사
IPC: G06F15/163
Abstract: A process transmission method according to an embodiment of the present invention comprises the steps of: allowing a process transmission server of a program to package a program to generate a process package including CPU register values related to the program; allowing the process transmission server to receive program request information from a client; and allowing the process transmission server to transmit the process package to the client, in response to the program request information. [Reference numerals] (AA) Process transmission server; (BB) Client; (S110) Generate a process package; (S120) Transmit program request information; (S130) Transmit the process package; (S140) Data process the process package and store the processed data in a main memory device; (S150) Transmit a CPU register value to a CPU when executing a process
Abstract translation: 根据本发明的实施例的处理传输方法包括以下步骤：允许程序的处理传输服务器打包程序以生成包括与程序相关的CPU寄存器值的处理程序包; 允许过程传输服务器从客户端接收节目请求信息; 并且响应于所述程序请求信息，允许所述处理传输服务器将所述处理包发送到所述客户端。 （附图标记）（AA）过程传输服务器; （BB）客户; （S110）生成流程包; （S120）发送节目请求信息; （S130）传送过程包; （S140）数据处理过程包并将处理的数据存储在主存储器中; （S150）执行进程时，向CPU发送CPU寄存器值
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公开(公告)号：KR1020130137310A
公开(公告)日：2013-12-17
申请号：KR1020120060777
申请日：2012-06-07
Applicant: 삼성전자주식회사
Inventor： 신현승
IPC: G06F13/00
CPC classification number: H04L25/14 , H04N21/4341
Abstract: An interface circuit includes a paralleling unit and a path changing unit. The paralleling unit parallels a serial signal received through a transmission line and outputs a plurality of reception parallel signals. The path changing unit detects a frame signal which periodically includes a frame code with a plurality of bits among the reception parallel signals and outputs a plurality of matching parallel signals to rearrange the reception parallel signals by changing the output path of the reception parallel signals based on the detection result.
Abstract translation: 接口电路包括并联单元和路径改变单元。 并联单元将通过传输线接收的串行信号并行并输出多个接收并行信号。 路径改变单元检测周期性地包括在接收并行信号中具有多个位的帧码的帧信号，并输出多个匹配并行信号，以通过基于接收并行信号的输出路径改变来重新排列接收并行信号 检测结果。
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Patent Agency Ranking
公开(公告)号：KR1020130001462A
公开(公告)日：2013-01-04
申请号：KR1020110062225
申请日：2011-06-27
Applicant: 삼성전자주식회사
CPC classification number: H04L67/1097
Abstract: PURPOSE: A look-up table logic device and a communicating server with the device are provided to disperse a load in a CPU of a server into high speed hardware logic, thereby reducing the load in the CPU. CONSTITUTION: Table identification(ID) processing units(71) are equipped corresponding to table ID and read response data for a request task from a storage unit. The table ID processing units output the response data as a packet. A control unit(75) distinguishes the table ID corresponding to the request task and outputs a turn-on signal to the table ID processing unit. A media access control processing unit(74) analyzes a task requested by a server and delivers the task to the control unit and outputs the packet to a client. The table ID processing unit includes registers storing a data size of the pack. [Reference numerals] (1) Server; (3) Client; (41) Local memory; (5) Network storage; (712) Size; (713) Start address; (714) End address; (715) Client address; (716) Storage address; (717) Counter; (718) Packet forming unit; (719) Data buffer; (72) Memory I/F; (74) MAC processing unit; (75) Control unit; (AA) Input interface
Abstract translation: 目的：提供查找表逻辑设备和与设备的通信服务器，以将服务器的CPU中的负载分散到高速硬件逻辑中，从而减少CPU中的负载。 规定：表识别（ID）处理单元（71）对应于来自存储单元的请求任务的表ID和读取响应数据。 表ID处理单元将响应数据作为数据包输出。 控制单元（75）区分与请求任务相对应的表ID，并将打开信号输出到表ID处理单元。 媒体访问控制处理单元（74）分析由服务器请求的任务，并将该任务传送到控制单元并将该分组输出给客户机。 表ID处理单元包括存储包的数据大小的寄存器。 （附图标记）（1）服务器; （3）客户; （41）本地记忆; （5）网络存储; （712）尺寸; （713）起始地址; （714）结束地址; （715）客户地址; （716）存储地址; （717）柜台; （718）分组形成单元; （719）数据缓存; （72）内存I / F; （74）MAC处理单元; （75）控制单元; （AA）输入接口
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公开(公告)号：KR101931566B1
公开(公告)日：2018-12-21
申请号：KR1020120060777
申请日：2012-06-07
Applicant: 삼성전자주식회사
Inventor： 신현승
IPC: G06F13/00
Abstract: 인터페이스 회로는 병렬화부 및 경로 전환부를 포함한다. 상기 병렬화부는 전송 라인을 통하여 수신되는 직렬 신호를 병렬화하여 복수의 수신 병렬 신호들을 출력한다. 상기 경로 전화부는 상기 수신 병렬 신호들 중에서 복수 비트의 프레임 코드를 주기적으로 포함하는 프레임 신호를 검출하고, 상기 검출 결과에 기초하여 상기 수신 병렬 신호들의 출력 경로를 전환하여 상기 수신 병렬 신호들을 재배열한 복수의 매칭 병렬 신호들을 출력한다.
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公开(公告)号：KR1020140040516A
公开(公告)日：2014-04-03
申请号：KR1020120107305
申请日：2012-09-26
Applicant: 삼성전자주식회사
Abstract: Suggested is a system which includes a CPU and a semiconductor memory device which includes a volatile memory which includes a volatile memory cell array and a nonvolatile memory which includes a nonvolatile memory cell array. Wherein, the volatile memory communicates with the CPU by a first interface. The nonvolatile memory communicates with the CPU by a second interface. [Reference numerals] (11) Central processing unit(CPU); (13) Memory controller; (14) Nonvolatile memory; (15) Volatile memory; (AA) MRS control
Abstract translation: 建议一种包括CPU和半导体存储器件的系统，其包括易失性存储器，其包括易失性存储器单元阵列和包括非易失性存储器单元阵列的非易失性存储器。 其中，易失性存储器通过第一接口与CPU通信。 非易失性存储器通过第二接口与CPU通信。 （附图标记）（11）中央处理单元（CPU）; （13）内存控制器; （14）非易失性存储器; （15）挥发性记忆; （AA）MRS控制
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公开(公告)号：KR1020120139129A
公开(公告)日：2012-12-27
申请号：KR1020110058737
申请日：2011-06-16
Applicant: 삼성전자주식회사
IPC: G06F13/16
CPC classification number: H04L69/12 , H04L69/324
Abstract: PURPOSE: A network memory access apparatus and method thereof are provided to flexibly overcome the limit of a memory capacity by using a network memory. CONSTITUTION: An MAC(medium access control) processing unit(30) is connected to a physical layer of a network. An MAC processing unit outputs a memory command by analyzing a frame received from the physical layer. A memory control unit(31) outputs first data received from the network to the network memory or outputs second data outputted from the network memory to the network. [Reference numerals] (23) Memory; (30) MAC processing unit; (31) Memory control unit; (32) Bust length counter; (33) Data conversion unit; (34) Memory clock buffer; (35) Command address buffer; (36, 37) Bust DQ buffer; (AA) Memory command; (BB,DD) Memory address; (CC) Error detection; (EE) Refresh/power down command
Abstract translation: 目的：提供一种网络存储器访问装置及其方法，以通过使用网络存储器灵活地克服存储器容量的限制。 构成：MAC（介质访问控制）处理单元（30）连接到网络的物理层。 MAC处理单元通过分析从物理层接收到的帧来输出存储器命令。 存储器控制单元（31）将从网络接收的第一数据输出到网络存储器，或者将从网络存储器输出的第二数据输出到网络。 （附图标记）（23）存储器; （30）MAC处理单元; （31）存储控制单元; （32）胸围计数器; （33）数据转换单元; （34）存储器时钟缓冲器; （35）命令地址缓冲区; （36,37）胸围DQ缓冲液; （AA）内存命令; （BB，DD）内存地址; （CC）错误检测; （EE）刷新/掉电命令
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