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    SRAM의 워드라인 드라이버
    4.
    发明授权
    SRAM의 워드라인 드라이버 失效
    SRAM的字线驱动器

    公开(公告)号：KR1019920001330B1

    公开(公告)日：1992-02-10

    申请号：KR1019890014944

    申请日：1989-10-17

    Applicant: 삼성전자주식회사

    Inventor： 이정렬

    IPC: G11C11/34

    Abstract: The wordline driver (20) of static random access memory for reducing a level of operation voltage of word lines comprises a gate (NG1) for receiving output signals (Wi,Ej) from a row address predecoder to output a selection signal for selecting a wordline, an inverter (I1) with a P type IGFET (T1) and a N type IGFET (T2) for inverting the output signal of the gate (NG1) in CMOS level and a IGFET (T23) having positive threshold voltage, a channel of which is connected between the inverter and one wordline of a memory cell array (100) and a gate of which is connected to a power supply terminal.

    Abstract translation: 用于降低字线的工作电压电平的静态随机存取存储器的字线驱动器（20）包括用于从行地址预解码器接收输出信号（Wi，Ej）的门（NG1），以输出用于选择字线 具有P型IGFET（T1）的反相器（I1）和用于反相CMOS电平的栅极（NG1）的输出信号和具有正阈值电压的IGFET（T23）的N型IGFET（T2），通道 其连接在反相器和存储单元阵列（100）的一个字线之间，其栅极连接到电源端子。

    반도체 메모리장치
    7.
    发明授权
    반도체 메모리장치 失效
    半导体存储器件

    公开(公告)号：KR1019910005586B1

    公开(公告)日：1991-07-31

    申请号：KR1019890003126

    申请日：1989-03-14

    Applicant: 삼성전자주식회사

    Inventor： 곽충근 ,  변현근 ,  이정렬 ,  전태수

    IPC: G11C8/00

    Abstract: The device replaces the fault cell array with the redundant cell array without the fuse and load cells in the address decoder so that the chip area may be reduced. The access time for selecting the redundant cell array may not be longer than selecting the normal one. The device comprises address free decoders providing the first and second free decoding signals, address decoders decoding the output of the second free decoding signal again and selecting the normal cell array with the enable signal, redundant free decoders supervising the states of the normal cell array, a controller controlling the address fee dcoders with the output of the redundant free decoder, and redundant decoders selecting the redundant cell array with the enable signal.

    Abstract translation: 该装置用冗余单元阵列代替故障单元阵列，而地址解码器中没有熔丝和负载单元，从而可以减少芯片面积。 选择冗余单元阵列的访问时间可能不比选择正常单元阵列的时间长。 该设备包括无地址解码器，提供第一和第二自由解码信号，地址解码器再次对第二自由解码信号的输出进行解码，并使用启用信号选择正常单元阵列，监控正常单元阵列的状态的冗余自由解码器， 控制地址费用转换器的控制器与冗余自由解码器的输出，以及冗余解码器，其使用启用信号选择冗余单元阵列。

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