公开(公告)号：KR1020040075515A

公开(公告)日：2004-08-30

申请号：KR1020030011046

申请日：2003-02-21

Applicant: 삼성전자주식회사

Inventor： 곽승현 ,  남승현 ,  정희도 ,  김석규 ,  안효주

IPC: H04B7/155

Abstract: PURPOSE: A data communication device and method between a base station modem and a decoder of a mobile communication system are provided to enhance data processing rate through effective data processing. CONSTITUTION: A decoder checks whether there is data to be decoded in modems(302). If there is data to be decoded, the decoder generates an address to be stored in a memory and inputs it to the modems(304). The decoder controls a DMI_WEZ(Data Management Interface_Write Enable Zero) terminal so that data can be inputted to the memory(306). The decoder controls the modems to output the data to the memory(308). The decoder determines whether data of every channel of the modems is outputted(310). If data of every channel is outputted, the decoder release the reading available state of the memory(312). The decoder releases the output available state of the modems(314).

Abstract translation: 目的：提供基站调制解调器和移动通信系统的解码器之间的数据通信设备和方法，以通过有效的数据处理来提高数据处理速率。 构成：解码器检查在调制解调器（302）中是否存在要解码的数据。 如果存在要解码的数据，则解码器产生要存储在存储器中的地址并将其输入到调制解调器（304）。 解码器控制DMI_WEZ（数据管理接口写入使能零）端子，以便可以将数据输入到存储器（306）。 解码器控制调制解调器将数据输出到存储器（308）。 解码器确定是否输出调制解调器的每个信道的数据（310）。 如果输出每个通道的数据，则解码器释放存储器的读取可用状态（312）。 解码器释放调制解调器的输出可用状态（314）。

公开(公告)号：KR1020050045766A

公开(公告)日：2005-05-17

申请号：KR1020030079942

申请日：2003-11-12

Applicant: 삼성전자주식회사

Inventor： 정희도 ,  김종돈

IPC: H04B7/15

CPC classification number: H03M13/276 ,  H03M13/2782

Abstract: 본 발명은 고속 패킷 데이터 통신 시스템에서 무선상의 버스트 에러에 견딜 수 있도록 전송 데이터를 소정 규칙에 따라 인터리빙하는 장치 및 방법에 관한 것이다. 제1 읽기 어드레스 발생기는 입력 부호심볼들 중 동기 채널의 부호심볼들을 읽어내기 위한 읽기 어드레스들을 발생하며, 제2 읽기 어드레스 발생기는 입력 부호심볼들 중 공통 전력제어 채널(CPCCH)의 부호심볼들을 읽어내기 위한 읽기 어드레스들을 발생한다. 부호심볼 인덱스 발생기는 입력 부호심볼들 중 상기 동기 채널이나 상기 CPCCH가 아닌 다른 채널들의 부호심볼들을 나타내는 부호심볼 인덱스들을 발생하고, BRO 인터리버는 상기 부호심볼 인덱스들에 해당하는 부호심볼들을 읽어내기 위한 읽기 어드레스들을 발생한다. 인터리빙 메모리는 부호심볼들을 수신하여 행의 순서로 저장하고 소정 인터리빙 규칙에 대응하는 상기 읽기 어드레스들에 따라 출력한다. 이러한 본 발명은 고속의 데이터 처리가 가능하고 인터리빙을 위한 여분의 메모리를 사용할 필요가 없으므로 하드웨어 리소스 측면에서도 효과적이다.

公开(公告)号：KR1020030069431A

公开(公告)日：2003-08-27

申请号：KR1020020009065

申请日：2002-02-20

Applicant: 삼성전자주식회사

Inventor： 정희도

IPC: H03M13/37

CPC classification number: H03M13/2957 ,  H03M13/6502

Abstract: PURPOSE: A turbo encoder for model ASIC(Application Specific Integrated Circuit) in a communication system and a turbo encoding method thereof are provided to enhance the efficiency of a turbo encoding operation by forming constantly a generating period of an address. CONSTITUTION: A turbo encoder for model ASIC in a communication system includes a preliminary processor(110), a register storage portion(120), a packet memory(140), an address generator(130), and a turbo encoder(150). The preliminary processor is used for calculating previously the erase interleaver address information according to an inputted turbo interleaver value. The register storage portion stores a predetermined value when the turbo interleaver address is not unerased. The packet memory is used for storing packet data. The address generator is used for reading the packet data according to the address information of the address storage portion and generating an address. The turbo encoder is used for performing a turbo encoding process for data according to the address of the address generator.

Abstract translation: 目的：提供一种用于通信系统中的ASIC（专用集成电路）的turbo编码器及其turbo编码方法，用于通过不断地形成地址的生成周期来提高turbo编码操作的效率。 构成：用于通信系统中的ASIC的turbo编码器包括预处理器（110），寄存器存储部分（120），分组存储器（140），地址生成器（130）和turbo编码器（150）。 预处理器用于根据输入的turbo交织器值先前计算擦除交织器地址信息。 当turbo交织器地址未被解除时，寄存器存储部分存储预定值。 分组存储器用于存储分组数据。 地址发生器用于根据地址存储部分的地址信息读取分组数据并产生一个地址。 turbo编码器用于根据地址发生器的地址对数据进行turbo编码处理。

公开(公告)号：KR1020010028710A

公开(公告)日：2001-04-06

申请号：KR1019990041093

申请日：1999-09-22

Applicant: 삼성전자주식회사

Inventor： 정희도 ,  강세진

IPC: H04W56/00 ,  H04L27/00

Abstract: PURPOSE: A PCM(Pulse Mode Modulation) data synchronization acquisition device and method in wireless local loop are provided to make synchronization of the demodulated data through a demodulator accord constantly in order to transmit it to PCM highway so as to prevent an abnormal PCM data decode caused by the discord of synchronization from removing. CONSTITUTION: The PCM(Pulse Mode Modulation) data synchronization acquisition device includes following units. A decoder(215) performs Viterbi decoding of the receiving signal with a predetermined unit period and generates an indication signal representing a unit period when the decoding is finished. A shift register(219) inputs the decoded data according to predetermined control. A control unit(213) controls that the decoded data is inputted to a shift register only when the setting bit of indication signal has the setting value and thereafter it is transmitted on PCM highway.

Abstract translation: 目的：提供无线本地环路中的PCM（脉冲模式调制）数据同步采集装置和方法，通过解调器使解调数据的同步不变，以便将其发送到PCM高速公路，以防止异常PCM数据解码 造成不同步的同步移除。 构成：PCM（脉冲调制）数据同步采集装置包括以下单元。 解码器（215）以预定的单位周期对接收信号进行维特比解码，并且生成表示解码结束时的单位周期的指示信号。 移位寄存器（219）根据预定的控制输入解码的数据。 只有当指示信号的设定位具有设定值，然后在PCM高速公路上传送时，控制单元（213）控制解码数据被输入到移位寄存器。

公开(公告)号：KR1020000056406A

公开(公告)日：2000-09-15

申请号：KR1019990005699

申请日：1999-02-20

Applicant: 삼성전자주식회사

Inventor： 정희도

IPC: H03M13/23

CPC classification number: H03M13/41 ,  H03M13/4169 ,  H03M13/6502

Abstract: PURPOSE: A trace-back method for a frame mode of viterbi decoder is provided to extract decoded value without using extra shift register. CONSTITUTION: A trace-back method for frame mode of viterbi decoder comprises the steps of; applying a trace-back signal from a control logic to a course metric memory(s1); performing trace-back by the trace-back signal(s2); revaluating the course metric value of respective state(s3); allocating the value for trace-forward by revaluation of step(s3)(s4-s5); allocating "0" when survivor course exists in higher than the trace-back signal(s6); allocating "1" when survivor course exists in lower than the trace-back signal(s7); transferring trace-forward signal to the course metric memory(s8); starting trace-forward when trace-back is finished(s9); advancing trace-forward based on allocated course metric value for trace-forward(s10); and outputting decoded value of advanced state every clock(s11).

Abstract translation: 目的：提供维特比解码器的帧模式的追溯方法，以提取解码值而不使用额外的移位寄存器。 构成：维特比解码器的帧模式的追溯方法包括以下步骤： 将跟踪信号从控制逻辑应用到路线度量存储器（s1）; 通过追溯信号执行追溯（s2）; 重新评估各州的课程度量值（s3）; 通过重新评估步骤（s3）（s4-s5）来分配追踪的价值; 当幸存者课程存在于跟踪信号（s6）以上时，分配“0”; 当幸存者课程存在于低于追溯信号（s7）时，分配“1”; 将跟踪前向信号传送到路线度量存储器（s8）; 回溯完成时启动跟踪（s9）; 基于分配的路线度量值进行跟踪前进（s10）; 并且每个时钟输出先进状态的解码值（s11）。