公开(公告)号：KR101578052B1

公开(公告)日：2015-12-17

申请号：KR1020080030780

申请日：2008-04-02

Applicant: 삼성전자주식회사

Inventor： 짠진펑 ,  김종선

IPC: H04N19/43

CPC classification number: H04N19/436 ,  H04N19/43 ,  H04N19/433

Abstract: 움직임추정장치및 이를구비하는동영상부호화장치가개시된다. 움직임추정알고리즘을수행하여움직임벡터를제공하는상기움직임추정장치의일예에따르면, 현재프레임의블록의화소데이터와기준프레임의탐색영역내의기준데이터에대한연산을수행하는복수의프로세싱엘레멘트(processing element)를구비하며, 상기탐색영역내의복수의후보블록(candidate block)에대한연산결과를병렬하게출력하는움직임추정부및 상기움직임추정부로부터제공된복수의연산결과를서로비교하고, 상기현재프레임의블록에대응하는움직임벡터를발생하여출력하는비교선택부를구비하는것을특징으로한다.

公开(公告)号：KR1020150141821A

公开(公告)日：2015-12-21

申请号：KR1020140070357

申请日：2014-06-10

Applicant: 삼성전자주식회사

Inventor： 짠진펑

IPC: G09G5/06

CPC classification number: G09G3/20 ,  G09G2320/0233 ,  G09G2320/0271 ,  G09G2320/0285 ,  G09G2330/10

Abstract: 본발명의하나의실시예에따른디스플레이장치는, 디스플레이장치는, 복수의픽셀을포함하는패널및 상기픽셀의불균일특성을보정하도록서로다른픽셀에대해다단계(multi-step)로보간수행하는불균일보정부를포함한다.

Abstract translation: 根据本发明的实施例，显示装置包括：面板，包括多个像素; 以及不均匀性校正单元，用于在多步骤中对不同像素执行内插以校正像素的不均匀性特性。

公开(公告)号：KR1020090105365A

公开(公告)日：2009-10-07

申请号：KR1020080030780

申请日：2008-04-02

Applicant: 삼성전자주식회사

Inventor： 짠진펑 ,  김종선

IPC: H04N19/43

CPC classification number: H04N19/436 ,  H04N19/43 ,  H04N19/433

Abstract: PURPOSE: A motion estimating apparatus and an animation encoding apparatus equipping the same are provided to supply suitable motion estimating device for processing an image of high data wideband and latency. CONSTITUTION: A motion estimation device(100) equips a motion estimation unit and a comparing selecting unit by performing a motion estimation algorithm. A motion estimation(170) equips a plurality of processing elements performing operation about a reference data within a searching area of the reference frame and pixel data of the block of the current frame. The motion estimation outputs it is the operation result about the candidate block of a plurality of in search area in a row.

Abstract translation: 目的：提供一种运动估计装置和动画编码装置，以提供用于处理高数据宽带和等待时间的图像的合适运动估计装置。 构成：运动估计装置（100）通过执行运动估计算法来配备运动估计单元和比较选择单元。 运动估计（170）装备有多个处理单元对参考帧的搜索区域和当前帧块的像素数据进行参考数据的操作。 运动估计输出是关于行中的多个搜索区域中的候选块的操作结果。

公开(公告)号：KR100801016B1

公开(公告)日：2008-02-04

申请号：KR1020070003262

申请日：2007-01-11

Applicant: 삼성전자주식회사

Inventor： 짠진펑 ,  김종선

IPC: G09G3/36 ,  G09G3/20 ,  G09G3/18 ,  G02F1/133

CPC classification number: G09G5/366 ,  G09G2320/0252 ,  G09G2320/0257 ,  G09G2320/0276 ,  G09G2320/103

Abstract: A semiconductor device having a correction parameter generator and a method for generating correction parameters are provided to extract the correction parameters on current pixels without the loss of clock by using memories having an LUT(Lookup Table). A semiconductor device includes an address generator(31) and an output unit. The address generator outputs plural addresses in response to first and second higher bits of the current and previous pixel values of the first and second selection bits, respectively. The output unit determines correction parameters corresponding to the addresses, selects index patterns in response to the first and second selection bits, aligns the determined correction parameters to correspond with the index patterns, and outputs the aligned correction parameters. The index patterns are generated from a lookup table having plural indexes according to the position of the correction parameters.

Abstract translation: 提供具有校正参数发生器和产生校正参数的方法的半导体器件，通过使用具有LUT（查找表）的存储器来提取当前像素上的校正参数而不损失时钟。 半导体器件包括地址发生器（31）和输出单元。 地址发生器分别响应于第一和第二选择位的当前和先前像素值的第一和第二较高位输出多个地址。 输出单元确定对应于地址的校正参数，响应于第一和第二选择位选择索引图案，将所确定的校正参数对齐于索引图案，并输出对准的校正参数。 索引图案根据校正参数的位置从具有多个索引的查找表生成。

公开(公告)号：KR100667595B1

公开(公告)日：2007-01-11

申请号：KR1020050133595

申请日：2005-12-29

Applicant: 삼성전자주식회사

Inventor： 짠진펑 ,  김종선 ,  이동열 ,  김범연

IPC: H03M7/40

CPC classification number: H03M7/40

Abstract: A variable length decoder is provided to obtain a low system clock and reduce power consumption by generating a plurality of symbols per a clock. A bit stream interface unit(210) generates a third bit stream to be used in a present decoding process by using a first bit stream which is not used in a previous decoding process and a second bit stream which is newly inputted. A decoding unit(220) generates a plurality of symbols per a clock by decoding the third bit stream in order to provide a fourth bit stream unused in the third bit stream to the bit stream interface unit. The bit stream interface unit obtains bits corresponding to the length of the bit stream used in the decoding process from the second bit stream and generates a third bit stream by accumulating the first bit stream and the bits.

Abstract translation: 提供可变长度解码器以获得低系统时钟并且通过每时钟产生多个符号来降低功耗。 比特流接口单元（210）通过使用在先前的解码处理中未使用的第一比特流和新输入的第二比特流来生成将在当前解码处理中使用的第三比特流。 解码单元（220）通过对第三比特流进行解码来生成每个时钟的多个符号，以便将第三比特流中未使用的第四比特流提供给比特流接口单元。 比特流接口单元从第二比特流获得与解码处理中使用的比特流的长度相对应的比特，并且通过累加第一比特流和比特来生成第三比特流。