公开(公告)号：KR1020050078704A

公开(公告)日：2005-08-08

申请号：KR1020040006463

申请日：2004-01-31

Applicant: 삼성전자주식회사

Inventor： 한동관

IPC: G11C29/00

CPC classification number: G01R31/318547 ,  G01R31/318563 ,  G11C29/40 ,  G11C29/56

Abstract: A scan based Automatic Test Pattern Generation (ATPG) test circuit, a test method using the test method, and a scan chain reordering method are disclosed. The test circuit tests for scan chains comprising unknown values which could adversely influence a test result. The test circuit uses a scan test point circuit to prevent unknown values from propagating through the test circuit, thus keeping the unknown values from influencing the test result. The reordering method is used where two scan chains comprising an unknown value exist in a single scan cycle so that the unknown values can be located during different clock cycles.

公开(公告)号：KR1020150144251A

公开(公告)日：2015-12-24

申请号：KR1020140086153

申请日：2014-07-09

Applicant: 삼성전자주식회사

Inventor： 한동관 ,  김지혜

IPC: G01R31/28 ,  G01R31/303

Abstract: 본발명의일실시예에따른 SOC(system on chip)는, 트리거신호에의해동작하는복수의스캔체인을포함하는적어도하나의코어(core), 상기복수의스캔체인중 적어도하나를선택하는지연대상선택신호및 상기트리거신호의지연정도를나타내는지연정도제어신호를생성하는지연컨트롤러및 상기지연대상선택신호및 지연정도제어신호에기초하여상기트리거신호를지연하여지연된트리거신호를상기복수의스캔체인으로제공하는지연신호생성부를포함하는것을특징으로한다.

Abstract translation: 根据本发明的实施例的片上系统（SOC）包括：至少一个核心，包括由触发信号操作的多个扫描链; 延迟目标选择信号，在多个扫描链中选择至少一个扫描链; 延迟控制器，生成表示触发信号的延迟量的延迟量控制信号; 延迟信号发生单元，通过基于延迟目标选择信号和延迟量控制信号延迟触发信号，向多个扫描链提供延迟的触发信号。

公开(公告)号：KR100448706B1

公开(公告)日：2004-09-13

申请号：KR1020020043354

申请日：2002-07-23

Applicant: 삼성전자주식회사

Inventor： 한동관

IPC: G11C29/00

CPC classification number: G01R31/318513 ,  G01R31/31705 ,  G01R31/318555 ,  G01R31/318558

Abstract: A system on chip and method of testing and/or debugging the same, where the system on chip includes a plurality of circuits and a control circuit for receiving a serial-parallel mode control signal and at least one selection signal externally input from one or more of a plurality of pins and outputting an output signal depending on values of the serial-parallel mode control signal and the at least one selection signal.

Abstract translation: 一种片上系统及其测试和/或调试方法，其中片上系统包括多个电路和控制电路，用于接收串并联模式控制信号和从一个或多个外部输入的至少一个选择信号 并根据串并行模式控制信号和至少一个选择信号的值输出输出信号。

公开(公告)号：KR1020170011449A

公开(公告)日：2017-02-02

申请号：KR1020150104097

申请日：2015-07-23

Applicant: 삼성전자주식회사

Inventor： 한주희 ,  임요섭 ,  한동관

IPC: G11C29/44 ,  G11C7/10

CPC classification number: G06F11/0793 ,  G06F11/073

Abstract: 복수의메모리블록들을포함하는집적회로의리페어정보제공장치는, 복수의메모리블록들에각각연결된복수의결함셀 어드레스레지스터들, 결함셀의어드레스및 메모리블록들중 결함셀을가지는메모리블록을나타내는메모리인덱스를포함하는리페어정보를저장하는리페어정보저장블록, 리페어정보저장블록으로부터리페어정보를독출하고, 독출된리페어정보에포함된결함셀의어드레스를결함셀 어드레스레지스터들각각에전송하고, 독출된리페어정보에포함된메모리인덱스에기초하여메모리블록선택신호를생성하는리페어정보제어블록, 및메모리블록선택신호에기초하여클록신호를결함셀 어드레스레지스터들중 결함셀을가지는메모리블록에연결된결함셀 어드레스레지스터에선택적으로전송하는클록게이팅블록을포함한다. 이에따라, 필요한리페어정보저장공간의사이즈가감소되고, 리페어정보로딩시간이감소되며, 리페어정보의재프로그래밍이가능하게될 수있다.

Abstract translation: 在包括多个存储块的集成电路中的修复信息提供装置分别包括连接到存储块的多个故障单元地址寄存器，修复信息存储块被配置为存储修复信息，该修复信息包括故障单元的地址和 存储器索引，指示具有故障单元的存储器块;修复信息控制块，被配置为从修复信息存储块读取修复信息，将修复信息中包括的故障单元的地址传送到各个故障单元地址寄存器;以及 基于修复信息中包含的存储器索引生成存储器块选择信号，以及时钟门控块，被配置为接收时钟信号，并且选择性地将时钟信号传送到连接到存储块的故障单元地址寄存器 响应于接收到存储块选择信号的故障小区。

公开(公告)号：KR1020130031022A

公开(公告)日：2013-03-28

申请号：KR1020110094680

申请日：2011-09-20

Applicant: 삼성전자주식회사

Inventor： 한동관

IPC: G01R31/28

CPC classification number: G06F11/273 ,  G01R31/31858 ,  G06F11/2236 ,  G06F11/263 ,  G06F11/267

Abstract: PURPOSE: A DUT test method, a DUT and a semiconductor device test system are provided to reduce the number of IO pins of a DUT required for a test. CONSTITUTION: A DUT(100) includes five IO pins, a chip level tap controller(10), a plurality of cores(20-1-20-M), a star controller(30) and a three phase buffer(40). Four IO pins receive a test input data signal, a test mode input signal, a clock signal and a reset signal and one output pin outputs test output data. The plurality of cores executes input signals applied from the input pins and individually output test output data. The chip level tap controller transmits a test command, test output data and an output enable signal based on the input signals. The star controllers calculates linear regression shift of the test input data signal and the test mode input signal in response to the clock signal and the reset signal. The star controller selects a test core and a test method in the plurality of cores based on a calculated first control value, performs a test and selects an output target DUT to output test output data based on a calculated second control value or a master bit. The three phase buffer outputs the test output data of the output target DUT based on the output enable signal.

Abstract translation: 目的：提供DUT测试方法，DUT和半导体器件测试系统，以减少测试所需的DUT的IO引脚数。 构成：DUT（100）包括五个IO引脚，芯片级抽头控制器（10），多个核（20-1-20-M），星控制器（30）和三相缓冲器（40）。 四个IO引脚接收测试输入数据信号，测试模式输入信号，时钟信号和复位信号，一个输出引脚输出测试输出数据。 多个核心执行从输入引脚施加的输入信号并单独输出测试输出数据。 芯片级抽头控制器根据输入信号发送测试命令，测试输出数据和输出使能信号。 星控制器根据时钟信号和复位信号计算测试输入数据信号和测试模式输入信号的线性回归偏移。 星控制器基于计算的第一控制值选择多个核心中的测试核心和测试方法，执行测试并选择输出目标DUT，以基于计算出的第二控制值或主位来输出测试输出数据。 三相缓冲器根据输出使能信号输出输出目标DUT的测试输出数据。

公开(公告)号：KR1020040009415A

公开(公告)日：2004-01-31

申请号：KR1020020043354

申请日：2002-07-23

Applicant: 삼성전자주식회사

Inventor： 한동관

IPC: G11C29/00

CPC classification number: G01R31/318513 ,  G01R31/31705 ,  G01R31/318555 ,  G01R31/318558

Abstract: PURPOSE: A single chip system and a test/debug method of the same are provided to reduce the number of pins in the single chip system embedded with a plurality of cores complying with IEEE1149.1. CONSTITUTION: The single chip system(300) comprises a test clock signal input pin, a test data input pin, a test mode signal input pin, a test reset signal input pin and a test data output pin. A plurality of cores(20,30) are designed according to IEEE1149.1 comprising the above pins. A control unit(50) inputs a fixed number of selection signals and a serial and parallel mode control signal applied from the external in response to a test clock signal applied from the test clock signal input pin, and outputs the inputted signals in response to the test reset signal applied from the test reset signal input pin. The first selection unit outputs test output data being output through one test data output port among the plurality of cores through the test data output pin in response to the selection signals. And the second selection unit outputs data being output from the first selection unit if the serial and parallel mode control signal indicates a parallel test mode, and outputs the test output data obtained by processing test input data by the cores if it indicates a serial test mode.

Abstract translation: 目的：提供单芯片系统及其测试/调试方法，以减少嵌入符合IEEE1149.1的多个内核的单芯片系统中的引脚数。 构成：单芯片系统（300）包括测试时钟信号输入引脚，测试数据输入引脚，测试模式信号输入引脚，测试复位信号输入引脚和测试数据输出引脚。 根据包括上述引脚的IEEE1149.1设计多个芯（20,30）。 控制单元（50）响应于从测试时钟信号输入引脚施加的测试时钟信号输入固定数量的选择信号和从外部施加的串行和并行模式控制信号，并且响应于 测试复位信号从测试复位信号输入引脚施加。 第一选择单元响应于选择信号通过测试数据输出引脚输出正在多个核心之间的一个测试数据输出端口输出的测试输出数据。 并且如果串行和并行模式控制信号指示并行测试模式，则第二选择单元输出从第一选择单元输出的数据，并且如果它指示串行测试模式，则输出由核心处理测试输入数据而获得的测试输出数据 。