公开(公告)号：KR1020020095357A

公开(公告)日：2002-12-26

申请号：KR1020010033551

申请日：2001-06-14

Applicant: 삼성전자주식회사

Inventor： 김경호 ,  최정환 ,  허락원

IPC: G06F13/00

CPC classification number: G11C11/409 ,  G11C7/1048 ,  G11C11/4076

Abstract: PURPOSE: An information processing system is provided to make the flight time of a clock signal identical to that of a data signal so that it can stably operate a Rambus DRAM mounted in a memory module though an operation frequency gets higher. CONSTITUTION: The system comprises a memory controller(110), and the first and second RIMM(Rambus in-line memory module, 120, 130). The memory controller(110) and the first and second RIMM(120, 130) are connected to a data bus(140), a clock line(150) and a reference voltage line(160). The clock line(150) has a closed loop structure comprising the first clock line segment(151) and the second clock line segment(152). Each clock line segments(151, 152) include a U-turn portion, the first terminal and the second terminal. The first terminals of both the clock line segments(151, 152) are commonly connected to a clock generator(170). The second terminals of both the clock line segments(151, 152) are connected to a terminal voltage via a terminal resistor. Accordingly, the distance between the clock generator(170) and the terminal resistor is identical to a length of the data bus(140), and each length of the clock line segments(151, 152) is also identical to a length of the data bus(140). As a result, the flight time of the clock signal gets identical to that of the data signal.

Abstract translation: 目的：提供一种信息处理系统，使时钟信号的飞行时间与数据信号的时间信号相同，使得它可以稳定地操作安装在存储器模块中的Rambus DRAM，尽管操作频率变高。 构成：系统包括存储器控制器（110）和第一和第二RIMM（Rambus在线存储器模块，120,130）。 存储器控制器（110）和第一和第二RIMM（120,130）连接到数据总线（140），时钟线（150）和参考电压线（160）。 时钟线（150）具有包括第一时钟线段（151）和第二时钟线段（152）的闭环结构。 每个时钟线段（151,152）包括U形转弯部分，第一端子和第二端子。 两个时钟线段（151,152）的第一个端子共同连接到一个时钟发生器（170）。 时钟线段（151,152）的第二端子通过端子电阻器连接到端子电压。 因此，时钟发生器（170）和端子电阻器之间的距离与数据总线（140）的长度相同，并且时钟线段（151,152）的每个长度也与数据的长度相同 总线（140）。 结果，时钟信号的飞行时间与数据信号的飞行时间相同。

公开(公告)号：KR100391990B1

公开(公告)日：2003-07-22

申请号：KR1020010033551

申请日：2001-06-14

Applicant: 삼성전자주식회사

Inventor： 김경호 ,  최정환 ,  허락원

IPC: G06F13/00

CPC classification number: G11C11/409 ,  G11C7/1048 ,  G11C11/4076

Abstract: An information processing system for controlling clock skew preferably includes a first and a second memory module, each of which has at last one semiconductor integrated circuit and is controlled by a chipset which can selectively control the time delay of an individual clock signal based on a stored value. The system further includes a clock line, which includes a first and a second clock line segment forming a closed loop and at least one data line connected between the chipset and a first termination device. By designing each of the first and the second clock line segments to be the same length as the data line, the propagation time of a clock signal and a data signal may be accurately matched.

Abstract translation: 用于控制时钟偏斜的信息处理系统优选地包括第一和第二存储器模块，其中的每一个具有至少一个半导体集成电路并且由芯片组控制，该芯片组可以基于所存储的信息选择性地控制单个时钟信号的时间延迟 值。 该系统还包括时钟线，其包括形成闭环的第一和第二时钟线段以及连接在芯片组和第一终端装置之间的至少一条数据线。 通过将第一和第二时钟线段中的每一个设计为与数据线相同的长度，可以精确地匹配时钟信号和数据信号的传播时间。

公开(公告)号：KR1020020040941A

公开(公告)日：2002-05-31

申请号：KR1020000070635

申请日：2000-11-25

Applicant: 삼성전자주식회사

Inventor： 허락원

IPC: G11C8/00

CPC classification number: G11C7/222 ,  G11C5/145 ,  G11C11/4076 ,  G11C11/4093

Abstract: PURPOSE: A register-controlled symmetrical delay locked loop(RSDLL) comprising a complex delay line is provided, which has a fast locking time and performs a fine tuning according to a phase variation, and reduces a delay line layout area to reduce power consumption in a DLL(Delay Locked Loop). CONSTITUTION: An input buffer(10) delays a system clock(CLK) in response to the system clock and outputs a buffered external clock(CLKin). A replica input buffer(60) is used in a feedback path for a transfer delay in the input buffer and a delay matching of an internal clock(CLKout). A phase detector(20) compares a relative phase difference between the external clock and the feedback clock signal(CLKout) delayed through a delay line(40), and outputs a shift left control signal(Shift-left) and a shift right control signal(Shift-right) to control a shift register(30). The shift register comprises a number of flip flops and outputs a control signal(DCON) to control a delay time of the delay line to the delay line. And the phase detector also outputs an up control signal(UP) and a down control signal(DOWN). A charge pump(50) outputs an analog control signal(VCON) to control the delay time of the delay line in response to the up or down control signal. The delay line performs a coarse locking in response to DCON, and performs a fine locking in response to VCON. An output buffer(70) outputs data(OUT_DAT) stored in a memory cell array by being synchronized to the internal clock.

Abstract translation: 目的：提供一种包括复数延迟线的寄存器控制的对称延迟锁定环路（RSDLL），具有快速的锁定时间，并根据相位变化执行微调，并减少延迟线布局面积，以降低功耗 一个DLL（延迟锁定环）。 构成：输入缓冲器（10）响应于系统时钟延迟系统时钟（CLK）并输出缓冲外部时钟（CLKin）。 复制输入缓冲器（60）用于输入缓冲器中的传输延迟的反馈路径和内部时钟（CLKout）的延迟匹配。 相位检测器（20）比较通过延迟线（40）延迟的外部时钟和反馈时钟信号（CLKout）之间的相对相位差，并输出左移位移控制信号（左移左移）和换档右控制信号 （Shift-right）来控制移位寄存器（30）。 移位寄存器包括多个触发器，并且输出控制信号（DCON）以控制延迟线到延迟线的延迟时间。 相位检测器还输出上升控制信号（UP）和下降控制信号（DOWN）。 电荷泵（50）输出模拟控制信号（VCON），以响应于上升或下降控制信号来控制延迟线的延迟时间。 延迟线响应于DCON执行粗略锁定，并响应于VCON执行精细锁定。 输出缓冲器（70）通过与内部时钟同步地输出存储在存储单元阵列中的数据（OUT_DAT）。