公开(公告)号：KR1020060114884A

公开(公告)日：2006-11-08

申请号：KR1020050037073

申请日：2005-05-03

Applicant: 서강대학교산학협력단

Inventor： 황선영 ,  이서훈 ,  유태현

IPC: H04L29/10

Abstract: An automatic generator of an interface circuit and an interface circuit embodied by the same are provided to improve convenience of a designer by inputting a design specification and information related to an IP(Intellectual Property) protocol through an input device implemented by a GUI(Graphic User Interface). In an automatic generator of an interface circuit, a design specification input unit(100) inputs a design specification of an interface circuit. An IP protocol input unit(300) inputs information related to the IP protocol. An interface circuit generator(250) includes an IP dual FSM(Finite State Machine)(430), a BUS dual FSM(410), and a dual port buffer(420). The IP dual FSM(430) communicates with the IP by being generated corresponding to the information related to the IP protocol. The BUS dual FSM(410) communicates with the BUS by being previously stored at a library. And, the dual port buffer(420) stores the data from the BUS dual FSM(410) or the IP and changes a storage capacity thereof.

Abstract translation: 提供了一种接口电路的自动发生器及其实现的接口电路，以通过输入设备规格和与IP（知识产权）协议有关的信息，通过GUI实现的输入设备（图形用户 接口）。 在接口电路的自动发生器中，设计规范输入单元（100）输入接口电路的设计规范。 IP协议输入单元（300）输入与IP协议有关的信息。 接口电路发生器（250）包括IP双FSM（有限状态机）（430），BUS双重FSM（410）和双端口缓冲器（420）。 IP双重FSM（430）通过与IP协议相关的信息生成相应的IP来进行通信。 BUS双重FSM（410）通过事先存储在库中与BUS进行通信。 并且，双端口缓冲器（420）存储来自BUS双重FSM（410）或IP的数据，并改变其存储容量。