公开(公告)号：KR101085155B1

公开(公告)日：2011-11-18

申请号：KR1020100113653

申请日：2010-11-16

Applicant: 서강대학교산학협력단

Inventor： 최우영 ,  이우준

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/78 ,  H01L21/335

CPC classification number: H01L29/7391 ,  H01L27/108 ,  H01L29/66356

Abstract: PURPOSE: A 1T DRAM cell device using a tunneling field effect transistor is provided to form a potential well on a body by inserting a separation semiconductor between a source or drain area and a body area. CONSTITUTION: A semiconductor active area(10) of a square pillar has a preset height. The semiconductor active area includes a source area(11), a semiconductor area(16), a body area(14), and a drain area(18). A potential well is formed in the body area and stores holes. A gate(31,32) is formed on two parallel sides of the semiconductor active area while interposing a gate insulation layer(20). A separation insulation layer is filled in two parallel sides of the semiconductor area.

Abstract translation: 目的：提供使用隧道场效应晶体管的1T DRAM单元器件，通过在源极或漏极区域与体区之间插入分离半导体来在主体上形成势阱。 构成：方柱的半导体有源区（10）具有预设高度。 半导体有源区域包括源极区域（11），半导体区域（16），体区域（14）和漏极区域（18）。 在身体区域形成潜在的井，并存储孔。 栅极（31,32）形成在半导体有源区域的两个平行侧上，同时插入栅极绝缘层（20）。 隔离绝缘层填充在半导体区域的两个平行侧上。