公开(公告)号：KR1020110023403A

公开(公告)日：2011-03-08

申请号：KR1020090081262

申请日：2009-08-31

Applicant: 에스케이하이닉스 주식회사 ,  서울대학교산학협력단

Inventor： 박지선 ,  차선용 ,  박병국 ,  김종필

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L29/4232 ,  H01L29/66583 ,  H01L29/7813

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to prevent alignment errors of a gate region and a source region by horizontally forming a drain region and the source region using a spacer. CONSTITUTION: A device isolation layer(102) defining an active region is formed on a semiconductor substrate(100). A gate material layer comprised of a gate insulation layer(104) and a gate conductive layer is formed on the semiconductor substrate. One side of the active region is exposed by etching the gate material layer. An LDD(Lightly Doped Drain) region(114) is formed on the drain region of one side of the exposed active region. The other side of the active region is exposed and a gate is formed by etching the gate material layer. A source region(122) is formed on the other side of the exposed active region.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过使用间隔物水平形成漏极区域和源极区域来防止栅极区域和源极区域的对准误差。 构成：在半导体衬底（100）上形成限定有源区的器件隔离层（102）。 在半导体衬底上形成由栅极绝缘层（104）和栅极导电层构成的栅极材料层。 通过蚀刻栅极材料层来暴露有源区的一侧。 在暴露的有源区的一侧的漏极区域上形成LDD（轻掺杂漏极）区域（114）。 有源区的另一侧被暴露，并且通过蚀刻栅极材料层形成栅极。 源区域（122）形成在暴露的有源区域的另一侧上。

公开(公告)号：KR1020110005185A

公开(公告)日：2011-01-17

申请号：KR1020090062763

申请日：2009-07-09

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김종필

IPC: H01L29/812 ,  H01L21/338

Abstract: PURPOSE: A tunneling field effect transistor(TFET) and a method for manufacturing the same are provided to reduce the length of a channel to be less than or equal to nano-scale sizes using a self-aligned process and a sidewall process. CONSTITUTION: A source(14) and a drain(12) are formed on the silicon layer of a silicon-on-insulator substrate to be spaced apart in a pre-set interval. The source is formed based on metal silicide. The drain is formed based on an n+ doping layer. A gate insulating layer(20) is formed on a channel region and the drain. A gate(32) is formed on the channel region. A first insulating film sidewall(50) is formed on the gate.

Abstract translation: 目的：提供隧道场效应晶体管（TFET）及其制造方法，以使用自对准工艺和侧壁工艺将沟道的长度减小到小于或等于纳米级尺寸。 构成：在绝缘体上硅衬底的硅层上形成源极（14）和漏极（12），以预定间隔间隔开。 源基于金属硅化物形成。 基于n +掺杂层形成漏极。 栅极绝缘层（20）形成在沟道区域和漏极上。 在沟道区上形成栅极（32）。 第一绝缘膜侧壁（50）形成在栅极上。

公开(公告)号：KR101030983B1

公开(公告)日：2011-04-28

申请号：KR1020090062763

申请日：2009-07-09

Applicant: 서울대학교산학협력단

Inventor： 박병국 ,  김종필

IPC: H01L29/812 ,  H01L21/338

Abstract: 본 발명은 비대칭 TFET의 구조 및 그 제조방법에 관한 것으로, 보다 상세하게는 자기 정렬된(self-aligned) 공정 및 측벽 공정을 통하여 나노 스케일의 짧은 채널을 갖고 소스를 금속 실리사이드로 형성함으로써, 소스와 채널 사이에 형성되는 쇼트키 장벽(Schottky barrier)을 이용한 TFET 및 그 제조방법에 관한 것이다.
비대칭, 쇼트키 장벽, TFET