公开(公告)号：KR1020030064111A

公开(公告)日：2003-07-31

申请号：KR1020020004556

申请日：2002-01-25

Applicant: 전자부품연구원

Inventor： 조삼구 ,  허일

IPC: H03H17/02

CPC classification number: H03H17/02 ,  H03H17/0291 ,  H03H17/0444 ,  H03H17/045 ,  H03H21/0012

Abstract: PURPOSE: A time divisional digital filter and a multi channel CODEC circuit by using the same are provided to perform a digital filtering the multi-channel digital signal with sharing a plurality of multiplier and a plurality of adders. CONSTITUTION: A time divisional digital filter includes a plurality of delay blocks(500,501,...50m), a multiplier block(510), an adder block(520) and a storage block(530). The plurality of delay blocks(500,501,...50m) is selectively operated in response to a plurality of switching signals and outputs a plurality of signals having a different plurality of delay values by delaying each of the input signals of the multi-channel in response to the each of the clock signals. The multiplier block(510) multiplies a plurality of delay signals outputted from a plurality of delay blocks(500,501,...50m) by a plurality of constants and the adder block(520) and adds the outputs of a plurality of multipliers. And, the storage block(530) divides the output signals of the adder block(520) in response to each of the channel and stores the divided signals.

Abstract translation: 目的：提供使用它们的时分数字滤波器和多通道CODEC电路，以共享多个乘法器和多个加法器来对多通道数字信号进行数字滤波。 构成：时分数字滤波器包括多个延迟块（500,501，... 50m），乘法器块（510），加法器块（520）和存储块（530）。 响应于多个切换信号选择性地操作多个延迟块（500,501，... 50m），并且通过将多通道的每个输入信号延迟，输出具有不同多个延迟值的多个信号 响应每个时钟信号。 乘法器块（510）将从多个延迟块（500,501，... 50m）输出的多个延迟信号乘以多个常数和加法器块（520），并将多个乘法器的输出相加。 并且，存储块（530）响应于每个信道划分加法器块（520）的输出信号，并存储划分的信号。