Abstract:
본 발명은 망막 또는 맥락막 내 혈관조영 광가간섭 단층촬영 장치 및 이를 이용한 질병 진단방법에 관한 것으로, 더욱 상세하게 조직의 저 관류를 빠르고 객관적으로 인지하여 패혈증과 같은 질병 또는 쇼크 상태를 조기에 진단할 수 있는 망막 및 맥락막 내 혈관조영 광가간섭 단층촬영 장치 및 이를 이용한 진단 방법에 관한 것이다.
Abstract:
본 발명은 망막 또는 맥락막 내 혈관조영 광가간섭 단층촬영 장치 및 이를 이용한 질병 진단방법에 관한 것으로, 더욱 상세하게 조직의 저 관류를 빠르고 객관적으로 인지하여 패혈증과 같은 질병 또는 쇼크 상태를 조기에 진단할 수 있는 망막 및 맥락막 내 혈관조영 광가간섭 단층촬영 장치 및 이를 이용한 진단 방법에 관한 것이다.
Abstract:
본 발명은 적응적 바이어스 회로 및 전력 증폭기에 관한 것으로, 상기 바이어스 회로는, 입력 신호의 포락선을 검출하는 포락선 검출부; 전원전압을 이용하여 소스전압을 생성하는 소스전압 생성부; 및 상기 전원전압과 상기 소스전압을 구동 전압으로 공급받아, 상기 포락선 검출부에서 검출된 포락선 신호를 증폭하여 제1 바이어스 전압을 생성하는 포락선 증폭부; 를 포함할 수 있다.
Abstract:
PURPOSE: A power amplifier is provided to increase linear output power and efficiency without reducing the total gain and reduce the size of a circuit. CONSTITUTION: A power amplifier (100) comprises a driving stage (110), a power stage (120) and a controlling part (130). The driving stage amplifies a signal to the level where the signal is set before. The power stage amplifies the power level of the amplified signal from the driving stage. The driving stage comprises a vector changing device (111), an amplification unit (112) and a vector coupler (113). The vector changing device transforms an input RF signal by vector transformation so that an I channel signal and a Q channel signal are provided. An amplifying unit comprises the first amplifier which amplifies the I channel signal to the set gain and the second amplifier which amplifies the Q channel signal to the set gain. [Reference numerals] (111) Vector changing device; (113) Vector coupler; (120) Power stage; (130) Controlling part; (AA) I channel control signal; (BB) I.Q channel control signal; (CC) Q channel control signal
Abstract:
There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively.
Abstract:
PURPOSE: A power amplifier is provided to increase the linearity of a power amplifier by minimizing a delay between the envelope information of an input signal which is offered to the amplifier circuit and the input signal which is offered to a bias circuit. CONSTITUTION: An envelope detector(110) includes a first resistance(R1), a first capacitor(C1), and a first NMOS FET(MN1). The envelope detector transfers a detection result to a bias power generator(120) by detecting the envelop component of an input signal. The bias power generator generates bias power which is varied according to the detection result of the envelope detector. An amplifier(140) outputs an output signal by amplifying the input signal according to the voltage level of the bias power which is supplied from the bias power generator. A low band pass filter(130) passes the bias power from the bias power generator through a preset base band.