Abstract:
PURPOSE: A three-dimensional stacked integrated circuit is provided to prevent damage of a package, by forming a plurality of penetration silicon vias at each edge of a plurality of semiconductor chips. CONSTITUTION: A plurality of semiconductor chips (110) is stacked on a base substrate (100). The semiconductor chips are conducted through a plurality of penetration silicon vias (210, 220). The penetration silicon vias are formed at each edge of the semiconductor chips. The penetration silicon vias are electrically connected to a conductive pattern. The conductive pattern is formed on the upper surface of the base substrate.
Abstract:
수동소자들이 적층된 반도체 칩은 기판, 활성층, 수동소자들 및 복수의 관통 실리콘 비아들을 포함한다. 활성층은 집적소자들, 전원 전압을 전달하는 파워 패턴들, 접지 전압을 전달하는 접지 패턴들 및 전기적 신호를 전달하는 신호 패턴들을 포함하며, 기판의 일면에 형성된다. 수동소자들은 기판의 타면에 적층된다. 복수의 관통 실리콘 비아들은 수동소자들 및 집적소자들이 전기적으로 연결되도록 기판을 관통하여 형성되며 이산화규소(SiO 2 )막으로 둘러싸인다. 복수의 관통 실리콘 비아들 중 일부는 수동소자들에 전원 전압을 전달하며, 복수의 관통 실리콘 비아들 중 나머지는 수동소자들에 접지 전압을 전달한다.
Abstract:
PURPOSE: A semiconductor chip with a passive device, a three dimensional multi chip including the same, and a three dimensional multi chip package including the same are provided to reduce power noise by electrically connecting the passive devices to the semiconductor chip. CONSTITUTION: A semiconductor chip with a passive device(130) includes a substrate, active layer, a passive device, and a plurality of through silicon vias. The active layer includes integrated devices, power patterns, ground patterns, and signal patterns(127) and is formed on one side of the substrate. A plurality of through silicon vias(114) passes through the substrate to electrically connect the passive device to the integrated device and is surrounded with SiO2. A part of through silicon vias transmits power voltage to the passive device. The remaining through silicon vias transmit the ground voltage to the passive devices.