公开(公告)号：KR1020080064261A

公开(公告)日：2008-07-09

申请号：KR1020070000970

申请日：2007-01-04

Applicant: 한국과학기술원

Inventor： 김정호 ,  이지왕 ,  김진국 ,  송익환 ,  조정현

IPC: H03K19/003

CPC classification number: H03K19/018521 ,  H03K5/133 ,  H04L25/0272

Abstract: A pre-emphasis output circuit is provided to perform a pre-emphasis operation without inputting an additional clock signal and recovering a clock of data because a plurality of delayers does not have the same delay time. In a pre-emphasis output circuit, a main driver(11) receives and amplifies a data signal, and outputs the data signal at an output terminal. A shared load(14) is connected to the output terminal of the main driver. A delay line(13) includes a plurality of delayers which are connected in series and control delay time according to a control voltage respectively, receives the data signals and outputs the delay signals to delay the data signals as much as the delay time, to each delayer. A plurality of tap drivers(121,122,123,124) amplify the delay signals and includes the pre-emphasis output circuit connected to add the delay signals at an output terminal of the main driver.

Abstract translation: 提供预加重输出电路以执行预加重操作，而不输入附加时钟信号并恢复数据时钟，因为多个延迟器不具有相同的延迟时间。 在预加重输出电路中，主驱动器（11）接收并放大数据信号，并在输出端输出数据信号。 共享负载（14）连接到主驱动器的输出端子。 延迟线（13）包括分别串联连接的多个延迟器和分别根据控制电压的控制延迟时间，接收数据信号并输出​​延迟信号以将延迟时间的数据信号延迟到每个延迟时间 延迟。 多个抽头驱动器（121,122,123,124）放大延迟信号，并且包括连接的预加重输出电路，以在主驱动器的输出端添加延迟信号。

公开(公告)号：KR100842775B1

公开(公告)日：2008-07-01

申请号：KR1020070014649

申请日：2007-02-13

Applicant: 한국과학기술원

Inventor： 김정호 ,  이지왕

IPC: H04L27/01 ,  H04B7/005 ,  H04B1/38 ,  H04B1/10

CPC classification number: Y02D70/40 ,  Y02D70/44 ,  H04L27/01 ,  H03G3/3042 ,  H04B1/38

Abstract: A two-stage equalizer, a two-stage equalization method, a receiver, and a high speed communication system are provided to decrease a power consumption of the communication system by effectively compensating for a high speed data signal. A two-stage equalizer includes an emphasis circuit(4100) and a de-emphasis circuit(4200). The emphasis circuit divides an input signal into N pieces. A divided signal passes through cascaded transconductance filters, such that a high frequency component is extracted. The signal from the transconductance filters passes through cascaded flat band amplifiers, such that delay times are equalized. The signal from the flat band amplifiers is amplified by a variable gain amplifier, such that a signal gain is adjusted. N amplified signals are added in a linear mixer.

Abstract translation: 提供两级均衡器，两级均衡器，接收器和高速通信系统，以通过有效地补偿高速数据信号来降低通信系统的功耗。 两级均衡器包括加重电路（4100）和去加重电路（4200）。 加重电路将输入信号分为N个。 分频信号通过级联跨导滤波器，从而提取高频分量。 来自跨导滤波器的信号通过级联的平带放大器，使得延迟时间相等。 来自平带放大器的信号由可变增益放大器放大，从而调整信号增益。 在线性混频器中加入N个放大的信号。

公开(公告)号：KR100811607B1

公开(公告)日：2008-03-11

申请号：KR1020060128023

申请日：2006-12-14

Applicant: 한국과학기술원

Inventor： 김정호 ,  이지왕

IPC: H01L23/12

CPC classification number: H01L2224/48091 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for tuning a passive element balun circuit is provided to reduce a cost and to simplify a tuning process by using a bonding wire having an adjustable length and an adjustable diameter. An integrated circuit(221) is mounted on an integrated circuit pad(222). A balun circuit(211) is mounted on a balun circuit pad(212) which is arranged at a front end of the integrated circuit. The integrated circuit pad and the balun circuit pad are integrated within a package. A method for tuning a passive element balun circuit includes a process for obtaining parasitic inductance and obtaining a length and a diameter of a necessary bonding wire(34,35,36,37) according to parasitic inductance, and a process for connecting electrically the balun circuit pad with the integrated circuit pad by using the bonding wires having electrical and magnetic characteristics corresponding to the length and the diameter.

Abstract translation: 提供了一种用于调谐无源元件平衡 - 不平衡转换电路的方法，以通过使用具有可调长度和可调节直径的接合线来降低成本并简化调谐过程。 集成电路（221）安装在集成电路板（222）上。 平衡 - 不平衡转换电路（211）安装在平衡 - 不平衡变换器电路板（212）上，该平衡 - 不平衡转换电路布置在集成电路的前端。 集成电路焊盘和平衡 - 不平衡转换电路板集成在封装内。 一种用于调谐无源元件平衡 - 不平衡转换电路的方法包括一种用于获得寄生电感并根据寄生电感获得所需接合线（34,35,36,37）的长度和直径的工艺，以及用于连接电子平衡 - 不平衡转换 电路板通过使用具有对应于长度和直径的电和磁特性的接合线而具有集成电路板。

公开(公告)号：KR100862233B1

公开(公告)日：2008-10-09

申请号：KR1020070000970

申请日：2007-01-04

Applicant: 한국과학기술원

Inventor： 김정호 ,  이지왕 ,  김진국 ,  송익환 ,  조정현

IPC: H03K19/003

Abstract: 프리엠퍼시스 출력 회로는 데이터 신호를 제공받아 증폭하고 출력 단자에서 출력하는 메인 드라이버, 상기 메인 드라이버의 출력 단자에 연결된 공유 부하, 지연선 및 상기 지연 신호들을 각각 제공받아 증폭하고, 지연 출력 신호들이 상기 메인 드라이버의 출력 단자에서 합산되도록 연결된 복수의 탭 드라이버들을 포함한다. 상기 지연선은 제어 전압에 따라 각각 지연 시간을 조절할 수 있는 복수의 직렬 연결된 지연기들을 포함하며, 상기 데이터 신호를 제공받아 상기 지연 시간만큼 상기 데이터 신호를 각각 지연한 지연 신호들을 상기 지연기들마다 각각 출력한다.