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公开(公告)号：KR101212633B1
公开(公告)日：2012-12-14
申请号：KR1020110073743
申请日：2011-07-25
Applicant: 한국과학기술원
CPC classification number: H03F3/211 , H01F27/2804 , H03F1/56 , H03F3/602 , H03F2200/541 , H03F2200/543
Abstract: PURPOSE: A combiner using a transmission line transformer is provided to reduce production costs of a transmitting terminal by comprising the combiner using the transmission line transformer in a wireless communication system. CONSTITUTION: A combiner using a transmission line transformer comprises first and second differential amplifiers(11,12), a transmission line transformer(20), and a matching unit(30). The first and the second differential amplifiers differentially amplify an input signal. The transmission line transformer comprises a first primary transmission line(21), a second primary transmission line(23), a second secondary transmission line(24), and a first secondary transmission line(22). The matching unit matches input impedances by connecting first resistance(31) to second resistance(32) between differential signal paths of a first differential amplifier and a second differential amplifier.
Abstract translation: 目的：提供使用传输线变压器的组合器，以通过在无线通信系统中使用传输线变压器包括组合器来降低发射终端的生产成本。 构成：使用传输线变压器的组合器包括第一和第二差分放大器（11,12），传输线变压器（20）和匹配单元（30）。 第一和第二差分放大器差分放大输入信号。 传输线变压器包括第一主传输线（21），第二主传输线（23），第二副传输线（24）和第一副传输线（22）。 匹配单元通过将第一电阻（31）连接到第一差分放大器和第二差分放大器的差分信号路径之间的第二电阻（32）来匹配输入阻抗。
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公开(公告)号：KR1020090005858A
公开(公告)日：2009-01-14
申请号：KR1020070069235
申请日：2007-07-10
Applicant: 한국과학기술원
IPC: H03F1/22
CPC classification number: H03F1/223 , H03F1/56 , H03F3/193 , H03F3/45188 , H03F2200/541 , H03F2200/543
Abstract: A cascode structure power amplifier using multiple common-gate transistor is provided to increase the efficiency and the power by enhancing the availability of the circuit configuration without the increment of the circuit size. Two common gate transistors(502) are parallelly connected to the drain of one common source transistor(501) and forms two pares of differential amplifier. Each differential amplifier pairs forms the output interface circuit. Differential input signals(501a,501b) are applied to the gate of the common source transistor. Amplifier is driven by authorizing gate bias voltages(502a, 502b) to the gate of the common gate transistor. Two primary side transmission lines(503,504) are matched to a secondary side transmission line(505) with the common gate transistor. Two primary side transmission lines deliver the electricity through the magnetic coupling. Two primary side transmission lines are selectively turned on and off. The gate bias voltage of the common gate transistor is individually controlled.
Abstract translation: 提供使用多个共栅极晶体管的共源共栅结构功率放大器，通过增加电路配置的可用性而不增加电路尺寸来提高效率和功率。 两个公共栅极晶体管（502）并联连接到一个公共源晶体管（501）的漏极，并形成两个差分放大器。 每个差分放大器对形成输出接口电路。 差分输入信号（501a，501b）被施加到公共源晶体管的栅极。 通过向栅极偏置电压（502a，502b）授权到公共栅极晶体管的栅极来驱动放大器。 两个初级侧传输线（503,504）与公共栅极晶体管与次级侧传输线（505）匹配。 两个初级侧传输线通过磁耦合传递电力。 选择性地打开和关闭两个初级侧传输线。 公共栅极晶体管的栅极偏置电压被单独控制。
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公开(公告)号：KR1020080109301A
公开(公告)日：2008-12-17
申请号：KR1020070057445
申请日：2007-06-12
Applicant: 한국과학기술원
CPC classification number: H03F1/223 , H03F1/56 , H03F3/193 , H03F3/211 , H03F2200/192
Abstract: A high frequency amplifier of cascade structure is provided to manufacture cost and to enhance availability of a circuit formation. A high frequency amplifier of cascade structure has transistors(401, 402, 403) which are connected to an output terminal. A transistor connected to the output terminal is parallel connected with a matching circuit fitting for a different operating frequency or a plurality of transistors in which a power coupling shift is connected. The transistor connected to the output terminal is selectively driven according to the operating frequency.
Abstract translation: 提供了级联结构的高频放大器来制造成本并提高电路形成的可用性。 级联结构的高频放大器具有连接到输出端的晶体管（401,402,403）。 连接到输出端子的晶体管与用于不同工作频率的匹配电路配件并联连接其中连接有功率耦合偏移的多个晶体管。 连接到输出端子的晶体管根据工作频率选择性地驱动。
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公开(公告)号：KR100882819B1
公开(公告)日：2009-02-10
申请号：KR1020070069235
申请日：2007-07-10
Applicant: 한국과학기술원
IPC: H03F1/22
Abstract: 본 발명은 공통 소스 트랜지스터와 공통 게이트 트랜지스터로 구성된 캐스코드 구조를 갖는 고주파 차동 증폭기에 관한 것으로서, 상기 공통 게이트 트랜지스터 하나에 상기 공통 소스 트랜지스터 복수개가 병렬로 연결되어 복수개의 차동쌍을 가지며, 상기 각 차동쌍은 개별적으로 정합회로를 이루는 것을 특징으로 한다. 본 발명에 의하면, 회로 구성의 복잡도를 줄이고 회로 크기의 큰 증가 없이 회로 구성의 활용도를 높이면서 고효율 및 고출력을 얻을 수 있다. 또한 출력전력의 조작을 더 용이하게 할 수 있다.
공통 게이트 트랜지스터, 증폭기, 정합회로, 캐스코드
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