公开(公告)号：KR100848578B1

公开(公告)日：2008-07-25

申请号：KR1020070030677

申请日：2007-03-29

Applicant: 한국전기연구원

Inventor： 허영 ,  진승오 ,  전성채 ,  김영희 ,  김태호 ,  이재형

IPC: H03K5/01

CPC classification number: H04N5/32 ,  H03K5/135 ,  H04N5/378 ,  H05G1/26

Abstract: A clock generator circuit of a single photon counter is provided to accurately count the number of photons incident on an image sensor by suppressing a short pulse clock from a counter clock. A delay unit(710) delays one of a Comp_OUT signal and a CLK_SEL signal, logically manipulates the Comp_OUT and CLK_SEL signals, and outputs a first manipulation signal. The Comp_OUT signal is an output signal from a comparator. The CLK_SEL signal is a clock select signal for counting digital pulses in the Comp_OUT signal. A logic manipulator(720) performs a logical manipulation on the Comp_OUT and CLK_SEL signals to generate a signal manipulation signal. A latch circuit unit(730) keeps a CLK_SET_OUT signal corresponding to the first and second manipulation signals and outputs the latched signal. A counter unit(740) counts the number of photons by using the Comp_OUT signal, the CLK_SEL_OUT signal, and a reset signal.

Abstract translation: 提供单个光子计数器的时钟发生器电路，以通过抑制来自计数器时钟的短脉冲时钟来精确地计数入射到图像传感器上的光子的数量。 延迟单元（710）延迟Comp_OUT信号和CLK_SEL信号中的一个，逻辑地操作Comp_OUT和CLK_SEL信号，并输出第一操作信号。 Comp_OUT信号是比较器的输出信号。 CLK_SEL信号是用于对Comp_OUT信号中的数字脉冲进行计数的时钟选择信号。 逻辑操纵器（720）对Comp_OUT和CLK_SEL信号执行逻辑操作以产生信号操纵信号。 锁存电路单元（730）保持对应于第一和第二操作信号的CLK_SET_OUT信号并输出​​锁存信号。 计数器单元（740）通过使用Comp_OUT信号，CLK_SEL_OUT信号和复位信号对光子的数量进行计数。