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Patent Agency Ranking
公开(公告)号：KR1019930002336B1
公开(公告)日：1993-03-29
申请号：KR1019900011200
申请日：1990-07-23
Applicant: 한국전자통신연구원
IPC: G06F15/16
Abstract: The circuit controls TAS (Test-And-Set) command to be achieved in one cycle for improved efficiency of pipe line and system. It includes a latched decoder (1) for analyzing given virtual memory, the 1st and 2nd setters (5,6) for sending latch data (LD0-1)(LD0-2) to writing buses (WBUS1,WBUS2), a RMW controller (4) for generating enable signals (OE1,OE2), and a multiplexer (7) for connecting one of the writing buses (WBUS1,WBUS2) to data bus (DATA).
Abstract translation: 电路控制TAS（测试和设置）命令在一个周期内实现，以提高管道和系统的效率。 它包括用于分析给定虚拟存储器的锁存解码器（1），用于将锁存数据（LD0-1）（LD0-2）发送到写入总线（WBUS1，WBUS2）的第一和第二设置器（5,6），RMW控制器 （OE1，OE2）和用于将写入总线（WBUS1，WBUS2）之一连接到数据总线（DATA）的复用器（7）。
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公开(公告)号：KR1019920003283B1
公开(公告)日：1992-04-27
申请号：KR1019890019678
申请日：1989-12-27
Applicant: 한국전자통신연구원
Inventor： 김인홍
IPC: G06F13/32
Abstract: The method is to handle the interrupt request from more than two interrupt requester. The method comprises steps: (A) receiving interrupt request transmitted from multiple CPUs; (B) generating selection signal by a interrupt request controller (1) according to the priorities of the CPUs; (C) forming a signal transmitting path between the selected CPU and system bus according to the selection signal; (D) receiving interrupt request from an interrupt handler adopter of different processor board; (E) generating a path selection signal related tothe interrupt request; and (F) setting the signal transmitting path between a system bus and a processor deposited at a processor board having the interrupt handler adopter (a).
Abstract translation: 该方法是处理来自两个以上中断请求者的中断请求。 该方法包括以下步骤：（A）接收从多个CPU发送的中断请求; （B）根据CPU的优先级由中断请求控制器（1）产生选择信号; （C）根据选择信号在选择的CPU和系统总线之间形成信号传输路径; （D）从不同处理器板的中断处理器采集器接收中断请求; （E）产生与所述中断请求相关的路径选择信号; 以及（F）在系统总线和存储在具有中断处理机采用者（a）的处理器板处理器的处理器之间设置信号传输路径。
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公开(公告)号：KR1019920002665B1
公开(公告)日：1992-03-31
申请号：KR1019890019503
申请日：1989-12-26
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The system includes a system bus cycle controller (7), a local bus cycle controller (2), a local arbiter (3), and a local memory (6). Checkings finds whether address phase signals and read signals are inputted, whether a signal representing the initiation of the data and a non-final data signal are inputted, whether a signal representing the start of the data phase and a signal (local- grant) are inputted, and whether a response signal (local stop) is inputted. In response to the respective inputs, control signals for write transactions are generated to control the local buses.
Abstract translation: 该系统包括系统总线周期控制器（7），本地总线周期控制器（2），本地仲裁器（3）和本地存储器（6）。 检查地址相位信号和读取信号是否被输入，表示数据的起始信号和非最终数据信号的信号是否表示数据相位开始的信号和信号（局部授权） 输入，以及是否输入响应信号（本地停止）。 响应于相应的输入，产生用于写入事务的控制信号以控制本地总线。
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