公开(公告)号：KR1020010063800A

公开(公告)日：2001-07-09

申请号：KR1019990061894

申请日：1999-12-24

Applicant: 한국전자통신연구원

Inventor： 문영수 ,  이경헌 ,  민병기

IPC: G06F15/02

Abstract: PURPOSE: An integrated operator for motion estimation is provided to decrease the number of hardwares and power consumption by processing various calculations of a motion estimation process in one device. CONSTITUTION: The first input terminal inputs the first pixel value. The second input terminal inputs the second pixel value. The third input terminal inputs a discriminated signal of a subtracting calculation and an adding calculation. The fourth input terminal inputs an input carry for a rounding calculation in reverse pixel motion estimation. A logical OR calculating unit(12) calculates the value inputted from the third input terminal and the value inputted from the fourth input terminal. The first exclusive-OR calculating unit(11) calculates the second pixel value inputted from the second input terminal and the value inputted from the third input terminal. The first adding unit(13) adds the first pixel value to the calculation result of the logical OR calculating unit and the calculation result of the first exclusive-OR calculating unit. The first logical AND calculating unit(15) calculates the reverse value of the output of the first adding unit and the signal inputted from the third input terminal. The second exclusive-OR calculating unit(16) calculates the calculation result of the first adding unit and the calculation result of the first logical AND calculating unit. A register(17) receives the calculation result of the second exclusive-OR calculating unit. The second logical AND calculating unit(14) calculates the reverse value of the input of the third input terminal and the calculation result of the first adding unit and applies the result to the most significant bit of the register. The first output terminal outputs the information of the register. The second adding unit(18) calculates data inputted from the fifth input terminal, the register and the first logical AND calculating unit, respectively. The output terminal outputs the calculation result of the second adding unit and transmits the result to the fifth input terminal.

Abstract translation: 目的：提供用于运动估计的综合运算器，通过处理一个设备中的运动估计过程的各种计算来减少硬件数量和功耗。 构成：第一个输入端输入第一个像素值。 第二输入端输入第二像素值。 第三输入端输入减法运算和加法运算的鉴别信号。 第四输入端输入反向像素运动估计中的舍入计算的输入进位。 逻辑或运算单元（12）计算从第三输入端输入的值和从第四输入端输入的值。 第一异或运算单元（11）计算从第二输入端子输入的第二像素值和从第三输入端子输入的值。 第一添加单元（13）将第一像素值与逻辑或计算单元的计算结果和第一异或运算单元的计算结果相加。 第一逻辑与计算单元（15）计算第一加法单元的输出和从第三输入端输入的信号的反向值。 第二异或计算单元（16）计算第一加法单元的计算结果和第一逻辑与计算单元的计算结果。 寄存器（17）接收第二异或运算单元的计算结果。 第二逻辑与计算单元（14）计算第三输入端子的输入的反向值和第一加法单元的计算结果，并将结果应用于寄存器的最高有效位。 第一个输出端输出寄存器的信息。 第二加法单元（18）分别计算从第五输入端子，寄存器和第一逻辑与计算单元输入的数据。 输出端子输出第二加法单元的计算结果，并将结果发送给第五输入端。

公开(公告)号：KR100315420B1

公开(公告)日：2001-11-28

申请号：KR1019990061894

申请日：1999-12-24

Applicant: 한국전자통신연구원

Inventor： 문영수 ,  이경헌 ,  민병기

IPC: G06F15/02

Abstract: 본발명은움직임추정과정의다양한연산을모두한 장치내에처리할수 있어하드웨어의수 및전력소모량을감소시킬수 있는움직임추정을위한통합연산장치에관한것으로, 정화소탐색, 반화소탐색, 인트라/인터모드결정등, 움직임추정과정에서필요한모든연산들을처리할수 있는통합연산장치를제공한다.