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Patent Agency Ranking
公开(公告)号：KR101077552B1
公开(公告)日：2011-10-28
申请号：KR1020070131487
申请日：2007-12-14
Applicant: 한국전자통신연구원
IPC: H03M13/11
CPC classification number: H03M13/116 , H03M13/1137 , H03M13/1185 , H03M13/1188 , H03M13/6516
Abstract: 이를위하여, 본발명은저밀도패리티검사부호의복호화장치에있어서, 패리티검사행렬을처리할부행렬크기및 병렬화수치에따라복수의기본패리티검사행렬을결정하기위한패리티검사행렬선택수단; 입력비트에대한대수근사화확률값을상기부행렬크기및 병렬화수치에따라입력받기위한비트입력수단; 상기패리티검사행렬을, 상기입력받은대수근사화확률값과상기결정된복수의기본패리티검사행렬을이용하여순차적으로부분병렬처리하기위한검사행렬처리수단; 및상기부분병렬처리된패리티검사행렬값으로부터비트레벨을판단하여상기부행렬크기및 병렬화수치에따라상기입력비트를복원하기위한비트처리수단을포함한다.
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公开(公告)号：KR1020090063948A
公开(公告)日：2009-06-18
申请号：KR1020070131487
申请日：2007-12-14
Applicant: 한국전자통신연구원
IPC: H03M13/11
CPC classification number: H03M13/116 , H03M13/1137 , H03M13/1185 , H03M13/1188 , H03M13/6516
Abstract: An apparatus and a method for decoding a low density parity check code using a plurality of basic parity check matrixes are provided to perform a decoding process at high speed while reducing complexity by partially processing a parity check matrix successively. A parity check matrix selecting unit(910) determines a plurality of basic parity check matrixes according to a size of sub-matrix and a paralleling number. A bit input unit(920) receives the log likelihood ratio value about the input bit according to a size of sub-matrix and the paralleling number. A check matrix processor(930) partially processes the parity check matrix successively by using the received log likelihood ratio value and the plurality of basic parity check matrixes. A bit processor restores the input bit according to the size of sub-matrix and the paralleling number by determining the bit level from the partially parallel processed parity check matrix value.
Abstract translation: 提供使用多个基本奇偶校验矩阵对低密度奇偶校验码进行解码的装置和方法，以通过连续地部分地处理奇偶校验矩阵来降低复杂度来高速地执行解码处理。 奇偶校验矩阵选择单元（910）根据子矩阵和平行数的大小来确定多个基本奇偶校验矩阵。 位输入单元（920）根据子矩阵和平行数的大小接收关于输入位的对数似然比值。 校验矩阵处理器（930）通过使用接收到的对数似然比值和多个基本奇偶校验矩阵来连续地处理奇偶校验矩阵。 位处理器通过从部分并行处理的奇偶校验矩阵值确定位电平，根据子矩阵的大小和并行数来恢复输入位。
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公开(公告)号：KR1020090059881A
公开(公告)日：2009-06-11
申请号：KR1020070126964
申请日：2007-12-07
Applicant: 한국전자통신연구원
CPC classification number: H04L7/0054 , H04L7/08 , H04W56/00 , H04W84/12
Abstract: A method and an apparatus for detecting a symbol boundary are provided to determine symbol synchronization according to a result by comparing a critical value with a difference between a previous detected peak value and a present detected peak value. A symbol synchronization device calculates a cross-correlation value about a received preamble(101). The symbol synchronization device searches a maximum peak value about a corrected real number component(102). A first peak value is stored in an A register(103). A second peak value is stored in a B register(104). A difference between the first peak value and the second peak value is calculated(105). An absolute value of the peak difference is compared with a first critical value for determining the first peak value as a symbol boundary(106). If the peak difference is less than the first critical value, the first peak value is compared with a second critical value for determining the first peak value as symbol synchronization(107). If the first peak value is larger than the second critical value, a position in which the first peak value is generated is determined as the symbol boundary for the symbol synchronization(108). If the first peak value is less than the second critical value, the second peak value is stored in the A register(109).
Abstract translation: 提供了用于检测符号边界的方法和装置，以便通过将临界值与先前检测到的峰值与当前检测到的峰值之间的差进行比较，根据结果来确定符号同步。 符号同步装置计算关于所接收的前导码的互相关值（101）。 符号同步装置搜索关于校正的实数分量（102）的最大峰值。 第一峰值存储在A寄存器（103）中。 第二峰值存储在B寄存器（104）中。 计算第一峰值和第二峰值之间的差值（105）。 将峰值差的绝对值与用于确定第一峰值作为符号边界的第一临界值进行比较（106）。 如果峰值差小于第一临界值，则将第一峰值与用于确定第一峰值作为符号同步的第二临界值进行比较（107）。 如果第一峰值大于第二临界值，则将产生第一峰值的位置确定为符号同步的符号边界（108）。 如果第一峰值小于第二临界值，则第二峰值存储在A寄存器（109）中。
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公开(公告)号：KR100924171B1
公开(公告)日：2009-10-28
申请号：KR1020070126964
申请日：2007-12-07
Applicant: 한국전자통신연구원
Abstract: 본 발명은 고속 데이터 전송을 위한 차세대 무선 근거리 통신 시스템에서 기존의 심볼 동기를 위한 피크 검출 방법의 문제점을 개선하여 신뢰성 있는 심볼 경계를 검출할 수 있는 심볼 경계 검출 방법 및 장치에 관한 것으로, 고속 무선 근거리 통신 시스템에서 심볼 동기를 위한 심볼 경계 검출 방법에 있어서, (a) 최대 피크치 검색에 의해 검색된 첫 번째 피크치(이전 피크치)와 두 번째 피크치(현재 피크치)의 차이를 계산하는 단계; (b) 상기 계산된 피크 차이와 제1 임계치(이는 이전 피크치를 심볼 경계로 결정하기 위해 임의로 설정된 값)를 비교하는 단계; (c) 상기 피크 차이가 상기 제1 임계치보다 작으면, 상기 이전 피크치가 발생된 위치를 심볼 경계로 결정하는 단계; 및 (d) 상기 피크 차이가 상기 제1 임계치보다 크면, 상기 현재 피크치가 발생된 위치를 심볼 경계로 결정하는 단계를 포함한다.
차세대, 고속, 무선, 근거리, 통신, WLAN, 심볼, 동기, 경계, 검출, 피크-
5.发明公开
公开(公告)号：KR1020090064709A
公开(公告)日：2009-06-22
申请号：KR1020070132008
申请日：2007-12-17
Applicant: 한국전자통신연구원
IPC: H03M13/11
CPC classification number: H03M13/116 , H03M13/1137 , H03M13/1185 , H03M13/618 , H03M13/6356 , H03M13/6393
Abstract: An apparatus and a method for generating a parity check matrix of an LDPC code and an LDPC encoding/decoding apparatus using the same are provided to perform a super speed decoding by designing an LDPC code supporting various information lengths and a code rate applying an information shortening method and a puncturing method. A first parity check matrix generating unit(31) generates a first parity check matrix comprised of a first information block and a parity block. A q-th parity check matrix generator generates the q-th parity check matrix by adding the q-th information block to the (q-1)-th parity check matrix. An information shortening unit(36) generates at least one parity check matrix different from the first to Q parity check matrixes by applying the information shortening to at least one parity check matrix among the first to Q parity check matrixes. A puncturing unit(37) generates at least one parity check matrix different from the first to Q parity check matrixes by applying a puncturing method to at least one parity check matrix among the first to Q parity check matrixes.
Abstract translation: 提供一种用于生成LDPC码的奇偶校验矩阵和使用其的LDPC编码/解码装置的装置和方法，用于通过设计支持各种信息长度的LDPC码和应用信息缩短的码率来执行超速解码 方法和打孔方法。 第一奇偶校验矩阵生成单元（31）生成由第一信息块和奇偶校验块构成的第一奇偶校验矩阵。 第q个奇偶校验矩阵发生器通过将第q个信息块添加到第（q-1）个奇偶校验矩阵来生成第q个奇偶校验矩阵。 信息缩短单元（36）通过在第一至Q奇偶校验矩阵中应用至少一个奇偶校验矩阵的信息缩短来生成与第一至第Q奇偶校验矩阵不同的至少一个奇偶校验矩阵。 打孔单元（37）通过对第一至第Q奇偶校验矩阵中的至少一个奇偶校验矩阵应用打孔方法，生成与第一至第Q奇偶校验矩阵不同的至少一个奇偶校验矩阵。
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