Abstract:
The two dimensional FFT (fast fourier transform) processor using the MSCM (mixed shuttle connection method) comprises: a butterfly operation circuit (1); a RAM (2) recording input/output data; a ROM (3) recording the coefficient for operation process; a first input/output register located between (1) and (2) for transmission of data; a second registers (4,5) located between (1) and (3) for transmission of the coefficient; a controller (6) for controlling the transmission of the operation control, data and coefficient; a first SISO (7); a second SISO (8) recording the multiple value provided from the first SISO; a SISO data output for outputting the data recorded at the second SISO; and address generator (10).