公开(公告)号：KR1020010018956A

公开(公告)日：2001-03-15

申请号：KR1019990035123

申请日：1999-08-24

Applicant: 한탁돈 ,  박우찬

Inventor： 한탁돈 ,  박우찬 ,  정철호

IPC: G06F7/49

Abstract: PURPOSE: A parallel floating point rounding method and its operation unit is provided to process an addition and a rounding operation in a floating point addition unit by one step and eliminate a Sticky bit in a critical path so that it can reduce a time delay occurred at an alignment of exponential numbers and enhance a process speed of a floating point addition operation. CONSTITUTION: The method comprises steps of comparing exponent parts of a 1st operand and a 2nd operand input by a user, aligning a fractional part by a difference between the exponent parts, logically adding a Sticky bit to the fractional part, executing an addition and a subtraction operation, executing 4 mode rounding operation on the addition and the subtraction result, selectively outputting the rounded value, and normalizing the selectively output rounded value. The Sticky bit is generated in the addition/subtraction and the rounding process, and has no effect on the critical path.

Abstract translation: 目的：提供一种并行浮点舍入方法及其操作单元，用于通过一步处理浮点加法单元的加法和舍入运算，消除关键路径中的粘滞位，从而可以减少发生在 指数数的对齐，并提高浮点加法运算的处理速度。 构成：该方法包括以下步骤：比较用户的第一操作数和第二操作数输入的指数部分，将小数部分与指数部分之间的差进行对齐，将粘滞位逻辑地添加到小数部分，执行加法和 减法运算，对相加和减法结果执行4模式舍入运算，选择性地输出舍入值，并对选择性输出的舍入值进行归一化。 粘滞位是在加法/减法和舍入过程中产生的，对关键路径没有影响。