公开(公告)号：AU6290186A

公开(公告)日：1987-04-09

申请号：AU6290186

申请日：1986-09-18

Applicant: ABB INC

Inventor： MACKENZIE RAYMOND WARREN

IPC: G01R21/00 ,  G01R21/127

Abstract: A shift register [Fig. 1 (20)] is utilized to provide a 90° delay in a pulse width modulated current signal [Fig. 2 (E)I to determine volt-amperes reactive. The shift register is associated with a clock (22) that provides a preselected frequency that, in combination with the number of stages in the shift register, delays the pulse width modulated current signal by an amount equivalent to one-quarter period (π/2) of the current waveform in the metered circuit. After delaying the pulse width modulated signal by 90°, the shifted signal is multiplied (24) by a voltage signal [Fig. 3 (G)] that represents the voltage in the metered circuit and the resulting product signal (Fig. 3 (1)] is input to a voltage-to-frequency converter (28).