Determining and compensating power transistor delay in parallel half bridge legs

    公开(公告)号:US10985751B2

    公开(公告)日:2021-04-20

    申请号:US16247112

    申请日:2019-01-14

    Applicant: ABB Schweiz AG

    Abstract: A method and an apparatus for determining switching delay times of power semiconductor switch components in parallel connected half bridge legs in which two or more power semiconductor switches are controlled in parallel. The method includes providing a gate control signal to gate drivers of the parallel connected power semiconductor switch components, determining collector to emitter voltages of the parallel connected power semiconductor switch components, and determining separate delay times for each of the parallel connected power semiconductor switch components based on the time instant of the gate control signal and the determined collector to emitter voltages or time derivatives of the determined collector to emitter voltages.

    DETERMINING AND COMPENSATING POWER TRANSISTOR DELAY

    公开(公告)号:US20190222210A1

    公开(公告)日:2019-07-18

    申请号:US16247112

    申请日:2019-01-14

    Applicant: ABB Schweiz AG

    CPC classification number: H02M1/088 H02M7/493

    Abstract: A method and an apparatus for determining switching delay times of power semiconductor switch components in parallel connected half bridge legs in which two or more power semiconductor switches are controlled in parallel. The method includes providing a gate control signal to gate drivers of the parallel connected power semiconductor switch components, determining collector to emitter voltages of the parallel connected power semiconductor switch components, and determining separate delay times for each of the parallel connected power semiconductor switch components based on the time instant of the gate control signal and the determined collector to emitter voltages or time derivatives of the determined collector to emitter voltages.

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