公开(公告)号：US20230179119A1

公开(公告)日：2023-06-08

申请号：US17541784

申请日：2021-12-03

Applicant: ABB Schweiz AG

Inventor： Eddy C. Aeloiza ,  Sayan Acharya ,  Utkarsh Raheja

IPC: H02M7/5387 ,  H02P27/06

CPC classification number: H02M7/53875 ,  H02P27/06

Abstract: An insulated gate field effect transistor (IGFET) based converter circuit is described that includes a direct current input comprising a high voltage input and a low voltage input, an IGFET gate input, and an equivalent phase leg comprising a plurality of parallel-connected cells. The parallel-connected cells each include: a first wide bandgap IGFET having a first drain electrode connected to the high voltage input, a first gate electrode connected to a first gate control input, and a first source electrode; a second wide bandgap IGFET having a second drain electrode connected to the first source electrode, a second gate electrode connected to a second gate control input, and a second source electrode connected to the low voltage input; and a step-inducing inductor coupled to: the first source electrode of the first wide bandgap IGFET, and an output node. The step-inducing inductor is connected to the output node.

公开(公告)号：US20230188134A1

公开(公告)日：2023-06-15

申请号：US17549520

申请日：2021-12-13

Applicant: ABB Schweiz AG

Inventor： Xiaoqing Song ,  Utkarsh Raheja ,  Pietro Cairoli ,  Sayan Acharya

IPC: H03K17/687 ,  H02H7/22 ,  H02H3/087

CPC classification number: H03K17/6874 ,  H02H7/22 ,  H02H3/087

Abstract: A gate driver circuit is provided that includes a turn-on path, a turn-off path, and a fast discharge path. The turn-on path is couplable between a gate of a solid-state switch and a voltage turn-on signal (VGON) from a gate driver, where the turn-on path defines a turn-on time for the solid-state switch. The turn-off path is couplable between the gate and a voltage turn-off signal (VGOFF) from the gate driver, where the turn-off path defines a turn-off time for the solid-state switch. The fast discharge path is selectively couplable in parallel with the turn-off path during a portion of a gate-to-source voltage (VGS) transition for the solid-state switch, where the turn-off path in parallel with the fast discharge path defines a turn-off delay for the solid-state switch and each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable.

公开(公告)号：US12119817B2

公开(公告)日：2024-10-15

申请号：US17549520

申请日：2021-12-13

Applicant: ABB Schweiz AG

Inventor： Xiaoqing Song ,  Utkarsh Raheja ,  Pietro Cairoli ,  Sayan Acharya

IPC: H03K17/687 ,  H02H3/087 ,  H02H7/22

CPC classification number: H03K17/6874 ,  H02H3/087 ,  H02H7/22

Abstract: A gate driver circuit is provided that includes a turn-on path, a turn-off path, and a fast discharge path. The turn-on path is couplable between a gate of a solid-state switch and a voltage turn-on signal (VGON) from a gate driver, where the turn-on path defines a turn-on time for the solid-state switch. The turn-off path is couplable between the gate and a voltage turn-off signal (VGOFF) from the gate driver, where the turn-off path defines a turn-off time for the solid-state switch. The fast discharge path is selectively couplable in parallel with the turn-off path during a portion of a gate-to-source voltage (VGS) transition for the solid-state switch, where the turn-off path in parallel with the fast discharge path defines a turn-off delay for the solid-state switch and each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable.

公开(公告)号：US11831251B2

公开(公告)日：2023-11-28

申请号：US17541784

申请日：2021-12-03

Applicant: ABB Schweiz AG

Inventor： Eddy C. Aeloiza ,  Sayan Acharya ,  Utkarsh Raheja

IPC: H02M7/5387 ,  H02P27/06

CPC classification number: H02M7/53875 ,  H02P27/06

Abstract: An insulated gate field effect transistor (IGFET) based converter circuit is described that includes a direct current input comprising a high voltage input and a low voltage input, an IGFET gate input, and an equivalent phase leg comprising a plurality of parallel-connected cells. The parallel-connected cells each include: a first wide bandgap IGFET having a first drain electrode connected to the high voltage input, a first gate electrode connected to a first gate control input, and a first source electrode; a second wide bandgap IGFET having a second drain electrode connected to the first source electrode, a second gate electrode connected to a second gate control input, and a second source electrode connected to the low voltage input; and a step-inducing inductor coupled to: the first source electrode of the first wide bandgap IGFET, and an output node. The step-inducing inductor is connected to the output node.