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    NON VOLATILE MEMORY CELL STRUCTURE USING MULTILEVEL TRAPPING DIELECTRIC
    2.
    发明申请
    NON VOLATILE MEMORY CELL STRUCTURE USING MULTILEVEL TRAPPING DIELECTRIC 审中-公开
    非挥发性记忆细胞结构使用多层次捕获电介质

    公开(公告)号：WO2003030264A1

    公开(公告)日：2003-04-10

    申请号：PCT/US2002/013573

    申请日：2002-04-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ZHENG, Wei ,  LI, Wenmei ,  HALLIYAL, Arvind ,  RANDOLPH, Mark, W.

    IPC: H01L29/51

    CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7923

    Abstract: A dielectric memory cell (10) comprises a substrate (12) which includes a source region (18), a drain region (20), and a channel region (22) positioned therebetween. A multilevel charge trapping dielectric (14) is positioned on the surface of the substrate (12) and a control gate (16) is positioned on the surface of the dielectric and is positioned over the channel region (22). The multilevel charge trapping dielectric (14) includes a tunneling dielectric (14a) adjacent to the substrate (12), a high dielectric constant capacitive coupling dielectric (14c) adjacent to the control gate (16), and a charge trapping dielectric layer (14b) positioned therebetween.

    Abstract translation: 介质存储单元（10）包括一个衬底（12），它包括一个源极区（18），一个漏极区（20）和一个位于它们之间的沟道区（22）。 多层电荷捕获电介质（14）位于衬底（12）的表面上，并且控制栅极（16）位于电介质的表面上并且位于沟道区（22）上方。 所述多电平电荷俘获电介质（14）包括与所述衬底（12）相邻的隧道电介质（14a），与所述控制栅极（16）相邻的高介电常数电容耦合电介质（14c）和电荷俘获介电层（14b） ）。

    RETROGRADE CHANNEL DOPING TO IMPROVE SHORT CHANNEL EFFECT
    5.
    发明申请
    RETROGRADE CHANNEL DOPING TO IMPROVE SHORT CHANNEL EFFECT 审中-公开
    改进通道，改善短路通道效果

    公开(公告)号：WO2004049453A1

    公开(公告)日：2004-06-10

    申请号：PCT/US2003/021682

    申请日：2003-07-10

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ZHENG, Wei ,  LIU, Zhizheng ,  RANDOLPH, Mark, W. ,  HE, Yi

    IPC: H01L29/788

    CPC classification number: H01L29/66825 ,  H01L29/105 ,  H01L29/7881 ,  H01L29/792

    Abstract: A memory semiconductor cell (30) comprises a gate region (16), a source region (14) and a drain region (14). A channel region (17) is formed between the source region (14) and the drain region (14). The channel region (17) comprises a first channel portion (33) with a first concentration of doping material, the first channel portion (33) disposed adjacent to an edge of the channel region (17) closest to and substantially parallel to the gate region (16). The channel region (17) further comprises a second channel portion (31) with a second concentration of doping material, the second channel portion (31) disposed substantially parallel to the first channel portion (33) and a third channel portion (32), disposed between the first channel portion (33) and the second channel portion (31), with a third concentration of doping material. The third concentration is lower than the first concentration and lower than the second concentration. The memory cell may be one of two general types of non-volatile memory, a floating gate cell or a nitride read only memory (NROM), whereby layer (12B) in a floating gate or a nitride layer respectively.

    Abstract translation: 存储器半导体单元（30）包括栅极区（16），源极区（14）和漏极区（14）。 在源极区域（14）和漏极区域（14）之间形成沟道区域（17）。 沟道区域（17）包括具有第一浓度掺杂材料的第一沟道部分（33），第一沟道部分（33）邻近沟道区域（17）的与栅极区域最接近且基本平行的边缘 （16）。 通道区域（17）还包括具有第二浓度掺杂材料的第二通道部分（31），第二通道部分（31）基本上平行于第一通道部分（33）和第三通道部分（32）设置， 设置在第一通道部分（33）和第二通道部分（31）之间，具有第三浓度的掺杂材料。 第三浓度低于第一浓度，低于第二浓度。 存储单元可以是两种一般类型的非易失性存储器，浮动栅极单元或氮化物只读存储器（NROM）中的一种，其中分别在浮动栅极或氮化物层中的层（12B）。

    POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL
    6.
    发明申请
    POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL 审中-公开
    用于补充位冲突改进和SONOS存储单元充电改进的POCKET IMPLAN

    公开(公告)号：WO2005078791A1

    公开(公告)日：2005-08-25

    申请号：PCT/US2004/042855

    申请日：2004-12-17

    Applicant: ADVANCED MICRO DEVICES, INC. ,  LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

    Inventor： LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

    IPC: H01L21/8246

    CPC classification number: H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

    Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is patterned and a pocket implant (630) is performed at an angle to establish pocket implants (620) within the substrate (602). A bitline implant (634) is then performed to establish buried bitlines (640) within the substrate (602). The patterned resist is then removed and the remainder of the charge trapping dielectric layer (608) is formed. A wordline material (660) is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines (662) that overlie the bitlines (640). The pocket implants (620) serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

    Abstract translation: 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 最初，电荷俘获电介质层（608）的一部分形成在衬底（602）上，并且在电荷俘获电介质层（608）的部分上形成抗蚀剂（614）。 对抗蚀剂（614）进行图案化，并且以一定角度执行凹穴注入（630）以在衬底（602）内建立凹穴注入（620）。 然后执行位线植入（634）以在衬底（602）内建立掩埋位线（640）。 然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层（608）。 字线材料（660）形成在电荷俘获电介质层的剩余部分上并被图案化以形成覆盖在位线（640）上的字线（662）。 口袋植入物（620）用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。 因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

    SILICON NITRADE CHARGE TRAPPING MEMORY DEVICE
    7.
    发明申请
    SILICON NITRADE CHARGE TRAPPING MEMORY DEVICE 审中-公开
    硅镍电池捕捉存储器件

    公开(公告)号：WO2004051753A1

    公开(公告)日：2004-06-17

    申请号：PCT/US2003/021676

    申请日：2003-07-10

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： RANDOLPH, Mark, W. ,  CHANG, Chi ,  HE, Yi ,  ZHENG, Wei ,  RUNNION, Edward, F.

    IPC: H01L29/792

    CPC classification number: H01L29/66833 ,  G11C16/0475 ,  G11C16/14 ,  H01L29/7923

    Abstract: The present invention is a method and system for erasing a nitride memory device. In one embodiment of the present invention, an isolated P-well (510) is formed in a semiconductor substrate (529). A plurality of N-type impurity concentrations (550, 555) are formed in the isolated P-well (510) and a nitride memory cell (560) is fabricated between two of the N-type impurity concentrations (550, 555). Finally, an electrical contact (590) is coupled to the isolated P-well (510).

    Abstract translation: 本发明是一种擦除氮化物存储器件的方法和系统。 在本发明的一个实施例中，在半导体衬底（529）中形成隔离的P阱（510）。 在隔离的P阱（510）中形成多个N型杂质浓度（550,555），并且在两种N型杂质浓度（550,555）之间制造氮化物存储单元（560）。 最后，电触点（590）耦合到隔离的P阱（510）。

    IMPROVED SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL
    8.
    发明申请
    IMPROVED SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL 审中-公开
    用于编程非易失性存储单元的改进系统

    公开(公告)号：WO2004051667A1

    公开(公告)日：2004-06-17

    申请号：PCT/US2003/023085

    申请日：2003-07-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： HE, Yi ,  LIU, Zhizheng ,  RANDOLPH, Mark, W. ,  HADDAD, Sameer, S.

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/0475 ,  G11C16/0491

    Abstract: An array (40) of dual bit dielectric memory cells (48) comprises a plurality of bit lines. A first bit line (201) forms a source region for each of a plurality of memory cells (38) within a column of memory cells within the array (40). A second bit line (202) forms a drain region for each of the plurality of memory cells (38) within the column. A channel region (50) of the opposite conductivity is positioned between the first bit line (201) and the second bit line (202) and forms a junction with each. A selected word line (211) is positioned over the channel region (50) and forms a gate (60) over each for a plurality of memory cells (48) within a same row. A plurality of non-selected word lines (210, 212), are each parallel to the selected word line (211) and each form a gate (60) over one of the plurality of memory cells (48) within the column other than the selected one of the plurality of memory cells (49). A word line control circuit (46) applies a positive programming voltage (220) to the selected word line (211) while a bit line control circuit (44) simultaneously applies a positive drain voltage to the drain bit line (202) and a positive source voltage to the source bit line (201), the positive source voltage being less than the positive drain voltage.

    Abstract translation: 双位介质存储器单元（48）的阵列（40）包括多个位线。 第一位线（201）为阵列（40）内的存储单元列内的多个存储器单元（38）中的每一个形成源区域。 第二位线（202）为列内的多个存储单元（38）中的每一个形成漏极区。 具有相反电导率的沟道区域（50）位于第一位线（201）和第二位线（202）之间，并且与第一位线形成结。 所选择的字线（211）位于信道区域（50）上方，并在同一行内的多个存储单元（48）上形成一个门（60）。 多个未选择的字线（210,212）各自平行于所选择的字线（211），并且每个在所述列内的多个存储器单元（48）中的一个上形成门（60），而不是 所选择的多个存储单元（49）中的一个。 字线控制电路（46）将正编程电压（220）施加到所选择的字线（211），同时位线控制电路（44）同时向漏位线（202）施加正漏电压， 源极电压（201），正电源电压小于正漏极电压。

    IMPROVED PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL
    9.
    发明申请
    IMPROVED PRE-CHARGE METHOD FOR READING A NON-VOLATILE MEMORY CELL 审中-公开
    用于读取非易失性存储器单元的改进的预充电方法

    公开(公告)号：WO2004051663A1

    公开(公告)日：2004-06-17

    申请号：PCT/US2003/023087

    申请日：2003-07-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： HE, Yi ,  LIU, Zhizheng ,  RANDOLPH, Mark, W. ,  RUNNION, Edward, F. ,  HAMILTON, Darlene ,  CHEN, Patu-Ling ,  LE, Binh, Q.

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C16/0475 ,  G11C16/24

    Abstract: A method of detecting a charge stored on a charge storage region (62) of a first dual bit dielectric memory cell (49) within an array (40) of dual bit dielectric memory cells (48) comprises coupling a first bit line (201) that forms a source junction with a channel region (50) of the first memory cell (49) to ground (68). A high voltage is applied to a gate (60) of the first memory cell (49) and to a second bit line (202) that is the next bit line to the right of the first bit line (201) and separated from the first bit line (201) only by the channel region (50). A third bit line (203), that is the next bit line to the right of the second bit line (202), is isolated such that its potential is effected only by its junctions with the a second channel region (50) and a third channel region (50) on opposing sides of the third bit line (203). A high voltage is applied to a pre-charge bit line that is to the right of the third bit line (203) and current flow is detected at the second bit line (202) to determine the programmed status of a source bit (62) of the first memory cell (49).

    Abstract translation: 检测存储在双位介质存储单元（48）的阵列（40）内的第一双位介质存储单元（49）的电荷存储区域（62）上的电荷的方法包括将第一位线（201） 其形成与第一存储单元（49）的沟道区（50）到地（68）的源极结。 向第一存储单元（49）的栅极（60）和第二位线（202）施加高电压，第二位线（202）是第一位线（201）右侧的下一个位线，并且与第一位线 位线（201）仅通过通道区域（50）。 作为第二位线（202）右侧的下一个位线的第三位线（203）是隔离的，使得其电位仅通过其与第二通道区域（50）的连接和第三位线 在第三位线（203）的相对侧上的通道区域（50）。 高电压被施加到位于第三位线（203）右侧的预充电位线，并且在第二位线（202）处检测电流以确定源位（62）的编程状态， 的第一存储单元（49）。

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