公开(公告)号：WO2002091462A1

公开(公告)日：2002-11-14

申请号：PCT/US2002/002995

申请日：2002-01-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LUKANC, Todd, P. ,  BELL, Scott, A. ,  LYONS, Christopher, F. ,  PLAT, Marina, V. ,  SUBRAMANIAN, Ramkumar

IPC: H01L21/768

CPC classification number: H01L21/76807

Abstract: A dual damascene process is described. A sacrificial post (124) is formed using a photolithographic process which may include photoresist (118) through a bright photomask (120). An interlevel dielectric (126), such as a low- k dielectric, is formed on the post (124), and a trench (128) etched exposing the post (124). The post (124) is then removed, thereby forming a hole (134). A conducting layer (136) is then formed in the hole (134) and the trench (128).

Abstract translation: 描述了双镶嵌工艺。 牺牲柱（124）使用光刻工艺形成，该光刻工艺可以通过光敏掩模（120）包括光致抗蚀剂（118）。 在柱（124）上形成诸如低k电介质的层间电介质（126），以及蚀刻暴露柱（124）的沟槽（128）。 然后将柱（124）移除，从而形成孔（134）。 然后在孔（134）和沟槽（128）中形成导电层（136）。

公开(公告)号：WO2002043140A3

公开(公告)日：2002-05-30

申请号：PCT/US2001/049460

申请日：2001-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUBRAMANIAN, Ramkumar ,  SINGH, Bhanwar ,  PLAT, Marina, V. ,  LYONS, Christopher, F.

IPC: H01L21/768

Abstract: A method of utilizing a bi-layer resist (110) to form contact holes, via and/or trenches between conductive layers. A bottom organic layer (130) of the bi-layer resist is formed, and then a silicon-containing top imaging layer (120) is formed on top of the lower layer. The top imaging layer is patterned to a desired pattern, using an etch chemistry which is etch-resistant to the lower layer. Since the top imaging layer is a thin layer, a precise pattern can be formed. The bottom organic layer is then patterned using the patterned upper layer as a hard mask, and using an etchant that is etch-resistant to the top imaging layer. The organic bottom layer remains in the semiconductor device as a low-k dielectric layer, and the top imaging layer may also remain, or may be removed, since it forms a dirty oxide layer that is useful in a providing conductive separation between conductive layers of a semiconductor device.

公开(公告)号：WO2007005362A2

公开(公告)日：2007-01-11

申请号：PCT/US2006/024765

申请日：2006-06-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  SPANSION LLC ,  SUBRAMANIAN, Ramkumar ,  SINGH, Bhanwar ,  PHAN, Khoi, A.

Inventor： SUBRAMANIAN, Ramkumar ,  SINGH, Bhanwar ,  PHAN, Khoi, A.

CPC classification number: G03F7/70341 ,  G03F7/70916 ,  G03F7/70925

Abstract: Disclosed are immersion lithography methods and systems involving irradiating a photoresist through a lens and an immersion liquid of an immersion lithography tool, the immersion liquid in an immersion space contacting the lens and the photoresist; removing the immersion liquid from the immersion space; charging the immersion space with a supercritical fluid; removing the supercritical fluid from the immersion space; and charging the immersion space with immersion liquid.

Abstract translation: 公开了浸入式光刻方法和系统，其涉及通过浸入式光刻工具的透镜和浸入液照射光致抗蚀剂，浸入式液体在与透镜和光致抗蚀剂接触的浸入空间中; 从浸没空间移除浸没液体; 用超临界流体填充浸没空间; 从浸没空间移除超临界流体; 并用浸没液体给浸没空间充电。

公开(公告)号：WO2003026000A1

公开(公告)日：2003-03-27

申请号：PCT/US2002/010826

申请日：2002-04-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： TABERY, Cyrus, E. ,  PHAN, Khoi, A. ,  RANGARAJAN, Bharath ,  SINGH, Bhanwar ,  SUBRAMANIAN, Ramkumar

IPC: H01L21/66

CPC classification number: G03F1/30 ,  G01N21/47

Abstract: A system for monitoring and controlling aperture etching in an alternating aperture phase shift mask (170, 270, 370, 722) is provided. The system includes one or more light sources (744, 762, 844), each light source (744, 762, 844) directing light to one or more apertures (150, 160, 250, 260, 350, 360, 430, 504, 506, 508, 604, 610, 612, 724, 824, 924) etched on a mask (420, 922). Light reflected from the apertures (150, 160, 250, 260, 350, 360, 430, 504, 506, 508, 604, 610, 612, 724, 824, 924) is collected by a measuring system (750, 850), which processes the collected light. The collected light is indicative of properties including the depth, width and/or profile of the openings on the mask (420, 922). The measuring system (750, 850) provides such depth, width and/or profile related data to a processor (760, 860, 1210) that determines the acceptability of the aperture (150, 160, 250, 260, 350, 360, 430, 504, 506, 508, 604, 610, 612, 724, 824, 924) and/or the mask (420, 922). The system also includes a plurality of etching devices (150, 160, 250, 260, 350, 360, 430, 504, 506, 508, 604, 610, 612, 724, 824, 924) in the mask (420, 922). The processor (760, 860, 1210) may selectively control the etching devices (450, 480) so as to regulate aperture etching.

Abstract translation: 提供了一种用于在交替孔径相移掩模（170,270,370,722）中监测和控制孔隙蚀刻的系统。 该系统包括一个或多个光源（744,762,844），每个光源（744,762,844）将光引导到一个或多个孔（150,160,250,260,350,360,430,504， 506,408,604,610,612,724,824,924）蚀刻在掩模（420,922）上。 从孔（150,160,250,260,350,360,430,504,506,508,604,610,612,724,824,924）反射的光由测量系统（750,850）收集， 它处理收集的光。 所收集的光指示包括掩模（420,922）上的开口的深度，宽度和/或轮廓的特性。 测量系统（750,850）向处理器（760,860,1210）提供这样的深度，宽度和/或轮廓相关数据，该处理器确定孔的可接受性（150,160,250,260,350,360,430 ，504,506,508,604,610,612,724,824,924）和/或掩模（420,922）。 该系统还包括掩模（420,922）中的多个蚀刻装置（150,160,250,260,350,360,430,504,506,508,604,610,612,724,824,924） 。 处理器（760,860,1210）可以选择性地控制蚀刻装置（450,480），以调节孔径蚀刻。

公开(公告)号：WO2003003123A3

公开(公告)日：2003-01-09

申请号：PCT/US2002/003020

申请日：2002-01-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SINGH, Bhanwar ,  TEMPLETON, Michael, K. ,  RANGARAJAN, Bharath ,  SUBRAMANIAN, Ramkumar

IPC: G03F7/20

Abstract: A system for monitoring a latent image exposed in a photo resist (300, 310, 675, 790) during semiconductor manufacture is provided. The system includes one or more light sources (110, 635, 740), each light source (110, 635, 740) directing light (760, 1602, 1712, 1840, 1940, 2040) to the latent image and/or one or more gratings exposed on one or more portions of a wafer (160, 400, 540, 665, 910, 1204, 1820, 1920, 2020). Light reflected (770, 1604, 1714, 1842, 1942, 2042) from the latent image and/or the gratings is collected by a signature system (630, 720), which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system (630, 720), which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.

公开(公告)号：WO2003003123A2

公开(公告)日：2003-01-09

申请号：PCT/US2002/003020

申请日：2002-01-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SINGH, Bhanwar ,  TEMPLETON, Michael, K. ,  RANGARAJAN, Bharath ,  SUBRAMANIAN, Ramkumar

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70675

Abstract: A system for monitoring a latent image exposed in a photo resist (300, 310, 675, 790) during semiconductor manufacture is provided. The system includes one or more light sources (110, 635, 740), each light source (110, 635, 740) directing light (760, 1602, 1712, 1840, 1940, 2040) to the latent image and/or one or more gratings exposed on one or more portions of a wafer (160, 400, 540, 665, 910, 1204, 1820, 1920, 2020). Light reflected (770, 1604, 1714, 1842, 1942, 2042) from the latent image and/or the gratings is collected by a signature system (630, 720), which processes the collected light. Light passing through the latent image and/or gratings may similarly be collected by the signature system (630, 720), which processes the collected light. The collected light is analyzed and can be employed to generate feedback information to control the exposure. The collect light is further analyzed and can be employed to generate feed forward information that can be employed to control post exposure processes including development and baking processes.

Abstract translation: 提供了一种用于在半导体制造期间监测在光致抗蚀剂（300,310,675,790）中暴露的潜像的系统。 该系统包括一个或多个光源（110,635,740），每个光源（110,635,740）将光（760,1602,1712,1840,1940,2040）引导到潜像和/或一个或多个 在晶片（160,400,540,665,910,1204,1820,1920,2020）的一个或多个部分上暴露的更多光栅。 从潜像和/或光栅反射的光（770,1604,1714,1842,1942,2042）由处理收集的光的签名系统（630,720）收集。 通过潜像和/或光栅的光可以类似地由处理收集的光的签名系统（630,720）收集。 收集的光被分析并且可以用于产生反馈信息以控制曝光。 收集的光进一步分析，并且可以用于产生可用于控制曝光后处理（包括显影和烘焙过程）的前馈信息。

公开(公告)号：WO2005045935A2

公开(公告)日：2005-05-19

申请号：PCT/US2004/031275

申请日：2004-09-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  LYONS, Christopher, F. ,  CHANG, Mark, S. ,  LOPATIN, Sergey, D. ,  SUBRAMANIAN, Ramkumar ,  CHEUNG, Patrick ,  NGO, Minh, Van ,  OGLESBY, Jane, V.

Inventor： LYONS, Christopher, F. ,  CHANG, Mark, S. ,  LOPATIN, Sergey, D. ,  SUBRAMANIAN, Ramkumar ,  CHEUNG, Patrick ,  NGO, Minh, Van ,  OGLESBY, Jane, V.

IPC: H01L27/115

CPC classification number: G11C11/5664 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L27/285 ,  H01L51/0595

Abstract: Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells (115) can have a bit line (610) of the wafer (806) as the first electrode (104, 1502) and operate with a second formed electrode (110, 1504) to activate a portion of an organic matter that is formed there between.

Abstract translation: 公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。 这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。 侧壁存储单元（115）可以具有作为第一电极（104,1502）的晶片（806）的位线（610）并且与第二形成的电极（110,1504）一起操作以激活有机物的一部分 之间形成的事物。

公开(公告)号：WO2004038787A2

公开(公告)日：2004-05-06

申请号：PCT/US2003/032656

申请日：2003-10-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHOO, Bryan, K. ,  SINGH, Bhanwar ,  SUBRAMANIAN, Ramkumar ,  RANGARAJAN, Bharath

IPC: H01L21/66

CPC classification number: H01L22/20 ,  G01N21/4738 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.

Abstract translation: 公开了用于监测和控制半导体制造工艺的系统和方法。 根据基于散射法的技术进行测量，该技术在晶片经历制造过程时在晶片上发生的电路结构中重复。 可以采用测量来产生可以用于选择性地调整一个或多个制造部件和/或与其相关联的操作参数以适应制造过程的前馈和/或反馈控制数据。 另外，例如，可以基于成本效益分析来确定是否丢弃晶片或其部分的测量。 在电路结构中的直接测量减轻了牺牲有价值的芯片的不动产，因为测试光栅结构可能不需要在晶片内形成，并且还有助于对实际影响芯片性能的元件的控制。

公开(公告)号：WO2003003413A3

公开(公告)日：2003-01-09

申请号：PCT/US2002/003021

申请日：2002-01-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUBRAMANIAN, Ramkumar ,  TEMPLETON, Michael, K. ,  SINGH, Bhanwar ,  RANGARAJAN, Bharath

IPC: H01L21/768

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features (18) are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features (18) in the inverse pattern image. The cooper features can be coated with a diffusion barrier layer and a dielectric (19). The dielectric (19) is polished to leave the dielectric filling the spaces between copper features (18). The invention provides copper lines and vias without the need for a dielectric or metal etching step. Another benefit of the invention is that lines widths can be increased by trimming the patterned coating prior to growing the copper features (18).

公开(公告)号：WO2005019935A2

公开(公告)日：2005-03-03

申请号：PCT/US2004/026716

申请日：2004-08-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  PHAN, Khoi, A. ,  RANGARAJAN, Bharath ,  SINGH, Bhanwar ,  SUBRAMANIAN, Ramkumar

Inventor： PHAN, Khoi, A. ,  RANGARAJAN, Bharath ,  SINGH, Bhanwar ,  SUBRAMANIAN, Ramkumar

IPC: G03F7/00

CPC classification number: G03F7/70341

Abstract: A system and/or method are disclosed for measuring (250) and/or controlling (260) refractive index (n) and/or lithographic constant (k) of an immersion medium (210) utilized in connection with immersion lithography. A known grating structure (602) is built upon a substrate (220). A refractive index monitoring component (340) facilitates measuring and/or controlling the immersion medium (210) by utilizing detected light scattered from the known grating structure (602).

Abstract translation: 公开了用于测量（250）和/或控制（260）浸入介质（210）的折射率（n）和/或光刻常数（k）的系统和/或方法， 与浸没式光刻的连接。 已知的光栅结构（602）建立在基底（220）上。 折射率监测部件（340）通过利用从已知光栅结构（602）散射的检测光来促进测量和/或控制浸没介质（210）。