公开(公告)号：JPH07202653A

公开(公告)日：1995-08-04

申请号：JP24002994

申请日：1994-10-04

Applicant: ADVANCED MICRO DEVICES INC

Inventor： BIN GUUO ,  AASAA HIYU

IPC: H03K5/13 ,  H03K19/0175

Abstract: PURPOSE: To eliminate the need for noise filtration and to attain accurate delay resolution by selectively delaying pulses during the operation of a common drain of a pair of CMOS field effect transistors(FETs). CONSTITUTION: A parallel variable resistor Ron and variable capacitors Con , Coff are substituted for a parallel n-channel MOS gate circuit connected between a node (mid) and a negative power supply VSS. Although a response at the trailing edge of an input step signal (fti) is delayed for a slight fixed time by an output step signal (fto), the delay does not depend upon a resistor Ron and a capacitor Con and is controlled by a dispersion type capacitor CD. A response at the leading edge of the signal (fti) depends upon the resistor Ron and a capacitor Con . When the resistor Ron is set to a maximum value, a delay value is maximized. When the resistor Ron is set to ten steps e.g. an incremental delay difference between respective steps becomes smaller than a nominal delay value and respective incremental time delay values are made equal. Thereby a controllable time delay value smaller than the delay of an inverter of one step can be obtained.